WM8753LEBSLASHV datasheet(32/87 Pages) WOLFSON

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Advanced Information

WM8753L

AI Rev 3.1 June 2004

The ALC function is enabled using the ALCSEL control bits. When enabled, the recording volume can

be programmed between –6dB and –28.5dB (relative to ADC full scale) using the ALCL register bits.

An upper limit for the PGA gain can be imposed by setting the MAXGAIN control bits.

HLD, DCY and ATK control the hold, decay and attack times, respectively:

Hold time is the time delay between the peak level detected being below target and the PGA gain

beginning to ramp up. It can be programmed in power-of-two (2

n) steps, e.g. 2.67ms, 5.33ms,

10.67ms etc. up to 43.7s. Alternatively, the hold time can also be set to zero. The hold time only

applies to gain ramp-up, there is no delay before ramping the gain down when the signal level is

above target.

Decay (Gain Ramp-Up) Time is the time that it takes for the PGA gain to ramp up across 90% of its

range (e.g. from –15B up to 27.75dB). The time it takes for the recording level to return to its target

value therefore depends on both the decay time and on the gain adjustment required. If the gain

adjustment is small, it will be shorter than the decay time. The decay time can be programmed in

power-of-two (2

n) steps, from 24ms, 48ms, 96ms, etc. to 24.58s.

Attack (Gain Ramp-Down) Time is the time that it takes for the PGA gain to ramp down across 90%

of its range (e.g. from 27.75dB down to -15B gain). The time it takes for the recording level to return

to its target value therefore depends on both the attack time and on the gain adjustment required. If

the gain adjustment is small, it will be shorter than the attack time. The attack time can be

programmed in power-of-two (2

n) steps, from 6ms, 12ms, 24ms, etc. to 6.14s.

When operating in stereo, the peak detector takes the maximum of left and right channel peak values,

and any new gain setting is applied to both left and right PGAs, so that the stereo image is preserved.

However, the ALC function can also be enabled on one channel only. In this case, only one PGA is

controlled by the ALC mechanism, while the other channel runs independently with its PGA gain set

through the control register.

When one ADC channel is unused or used for DC measurement, the peak detector disregards that

channel. The ALC function can also operate when the two ADC outputs are mixed to mono in the

digital domain, but not if they are mixed to mono in the analogue domain, before entering the ADCs.

ALCSR is used to set the sample rate for the ALC when the ADC is in voice mode (SRMODE=1).

When ALC is enabled in voice mode the ALCSR bits should be set to match the ADC sample rate as

shown in Table 20.

ADC SAMPLE RATE

ALCSR [3:0]

8kHz

0110

11.025/12kHz

1000

16kHz

1010

22.05kHz

1010

32kHz

1100

48/44/1kHz

0000

88.2/96kHz

1110

Table 20 ADC Sample Rate

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