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L99DZ120 データシート(PDF) 16 Page - STMicroelectronics |
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L99DZ120 データシート(HTML) 16 Page - STMicroelectronics |
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16 / 162 page  Block diagram and pin descriptions L99DZ120 16/162 DocID029145 Rev 4 53 NINT Interrupt output (low active; push-pull output stage) to indicate VSREG early warning (Active mode); indicates wake-up events from V1_standby mode 54 NC Not connected 55 NC Not connected 56 Debug Debug input to deactivate the window watchdog (high active) 57 LIN LIN bus line 58 5V_2 Voltage regulator 2 output: 5 V supply for external loads (potentiometer, sensors). V2 is protected against reverse supply 59 GL1 Gate driver for PowerMOS low-side switch in half-bridge 1 60 SH1 Source of high-side switch in half-bridge 1 61 GH1 Gate driver for PowerMOS high-side switch in half-bridge 1 62 GH2 Gate driver for PowerMOS high-side switch in half-bridge 2 63 SH2 Source of high-side switch in half-bridge 2 64 GL2 Gate driver for PowerMOS low-side switch in half-bridge 2 Table 1. Pin definitions and functions (continued) Pin Symbol Function |
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