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STA321MPL1 データシート(PDF) 70 Page - STMicroelectronics |
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STA321MPL1 データシート(HTML) 70 Page - STMicroelectronics |
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70 / 80 page  Configuration registers (0x77; 0x78; 0x79) STA321MPL1 70/80 DocID029389 Rev 1 6.5.10 Clock manager configuration PLL configuration registers (0x71, 0x72, 0x73, 0x74) PLL multiplication factor (fractional part, H) (0x71) PLL multiplication factor (fractional part, L) (0x72) PLL multiplication factor (integral part) named as N Division Factor (NDIV) and dithering (0x73) D7 D6 D5 D4 D3 D2 D1 D0 PLLFI[15:8] 00 000 00 0 D7 D6 D5 D4 D3 D2 D1 D0 PLLFI[7:0] 00 000 00 0 D7 D6 D5 D4 D3 D2 D1 D0 PLLDD[1:0] PLLND[5:0] 00 000 00 0 Bit RW RST Name Description 7 RW 0 PLLDD1 PLL dithering: 00: PLL clock dithering disabled 01: PLL clock dithering enabled (triangular) 10: PLLclock dithering enabled (rectangular) 11: reserved 6 RW 0 PLLDD0 5 RW 0 PLLND5 N (loop) Division Factor This factor should be: 4 RW 0 PLLND4 3 RW 0 PLLND3 2 RW 1 PLLND2 1 RW 0 PLLND1 0 RW 1 PLLND0 5N ≤ DIV 55 ≤ |
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