MAS3587F datasheet(43/82 Pages) MICRONAS

43 / 82 page

ADVANCE INFORMATION

MAS 3587F

Micronas

3.4.3. Codec Registers

Table 3–12: Codec control registers on I2C subaddress 6Chex

Address

(hex)

Function

Name

CONVERTER CONFIGURATION

00 00

Audio Codec Configuration

0 dB is related to the D/A full-scale output voltage

(Please refer to Section 4.6.4. on page 72)

bit[15:12]

A/D converter left amplifier gain = n*1.5

−3 [dB]

bit[11:8]

A/D converter right amplifier gain = n*1.5

−3 [dB]

1111

+19.5 dB

1110

+18.0 dB

...

0011

+1.5 dB

0010

0.0 dB

0001

−1.5 dB

0000

− 3.0 dB

bit[7:4]

Microphone amplifier gain = n*1.5+21 [dB]

1111

+43.5 dB

1110

+42.0 dB

...

0001

+22.5 dB

0000

+21.0 dB

bit[3]

Input selection for left A/D converter channel

line-in

microphone

bit[2]

Enable left A/D converter1)

bit[1]

Enable right A/D converter1)

bit[0]

Enable D/A converter1)

CONV_CONF

1) The generation of the internal DC reference voltage for the D/A converter is

also controlled with this bit. In order to avoid click noise, the reference voltage

at pin AGNDC should have reached a near ground potential before repower-

ing the D/A converter after a short down phase.

Alternatively at least one of the A/D converters (bits [2] or [1]) should remain

set during short power-down phases of the D/A. Then the DC reference volt-

age generation for the D/A converter will not be interrupted.

INPUT MODE SELECT

00 08

Input Mode Setting

bit[15]

Mono switch

stereo input mode

left channel is copied into the right channel

bit[14:2]

Reserved, must be set to 0

bit[1:0]

Deemphasis select

deemphasis off

deemphasis 50 µs

deemphasis 75 µs

ADC_IN_MODE

MAS3587F データシート(PDF) 43 Page - Micronas

MAS3587F データシート(HTML) 43 Page - Micronas

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82

データシートダウンロード