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WM8196 データシート(PDF) 10 Page - Cirrus Logic |
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WM8196 データシート(HTML) 10 Page - Cirrus Logic |
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10 / 32 page ![]() WM8196 Production Data w PD Rev 4.6 October 2008 10 SERIAL INTERFACE SCK SDI SEN SDO t SPER t SCKL tSCKH t SSU t SH t SCE t SEW t SEC t SERD t SCRD MSB LSB t SCRDZ ADC DATA ADC DATA REGISTER DATA Figure 5 Serial Interface Timing Test Conditions AVDD = DVDD1 = 5.0V, DVDD2 = 3.3V, AGND = DGND = 0V, TA = 25 °C, MCLK = 24MHz unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS SCK period tSPER 41.6 ns SCK high tSCKH 18.8 ns SCK low tSCKL 18.8 ns SDI set-up time tSSU 6 ns SDI hold time tSH 6 ns SCK to SEN set-up time tSCE 12 ns SEN to SCK set-up time tSEC 12 ns SEN pulse width tSEW 25 ns SEN low to SDO = Register data tSERD 30 ns SCK low to SDO = Register data tSCRD 30 ns SCK low to SDO = ADC data tSCRDZ 30 ns Note: 1. Parameters are measured at 50% of the rising/falling edge |
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