WM8196 datasheet(27/32 Pages) CIRRUS

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WM8196

Production Data

PD Rev 4.6 October 2008

The following table describes the function of each of the control bits shown in Table 6.

BIT

NAME(S)

DEFAULT

DESCRIPTION

When SELPD = 1 this bit has no effect.

When SELPD = 0 this bit controls the global power down:

0 = complete power down, 1 = fully active.

CDS

Select correlated double sampling mode: 0 = single ended mode,

1 = CDS mode.

MONO

Mono/colour select: 0 = colour, 1 = monochrome operation.

SELPD

Selective power down: 0 = no individual control,

1 = individual blocks can be disabled (controlled by SELDIS[3:0]).

Offsets PGA output to optimise the ADC range for different polarity sensor

output signals. Zero differential PGA input signal gives:

5:4

PGAFS[1:0]

00 = Zero output

(use for bipolar video)

01 = Zero output

10 = Full-scale positive output

(use for negative going video)

11 = Full-scale negative output

(use for positive going video)

MODE4

Required when operating in MODE4: 0 = other modes, 1 = MODE4.

Setup

Reserved

Must be set to zero

Determines the output data format.

1:0

MUXOP[1:0]

00 = 16-bit parallel

01 = 8-bit multiplexed (8+8 bits)

10 = 8-bit multiplexed mode (8+8 bits)

11 = 4-bit multiplexed mode (4+4+4+4 bits)

INVOP

Digitally inverts the polarity of output data.

0 = negative going video gives negative going output,

1 = negative-going video gives positive going output data.

VRLCEXT

When set powers down the RLCDAC, changing its output to Hi-Z, allowing

VRLC/VBIAS to be externally driven.

RLCDACRNG

Sets the output range of the RLCDAC.

0 = RLCDAC ranges from 0 to AVDD (approximately),

1 = RLCDAC ranges from 0 to VRT (approximately).

Sets the output latency in ADC clock periods.

1 ADC clock period = 2 MCLK periods except in Mode 3 where 1 ADC clock

period = 3 MCLK periods.

Setup

7:6

DEL[1:0]

00 = Minimum latency

01 = Delay by one ADC clock

period

10 = Delay by two ADC clock periods

11 = Delay by three ADC clock periods

3:0

RLCV[3:0]

1111

Controls RLCDAC driving VRLC pin to define single ended signal reference

voltage or Reset Level Clamp voltage. See Electrical Characteristics section

for ranges.

CDS mode reset timing adjust.

5:4

CDSREF[1:0]

00 = Advance 1 MCLK period

01 = Normal

10 = Retard 1 MCLK period

11 = Retard 2 MCLK periods

Monochrome mode channel select.

Setup

7:6

CHAN[1:0]

00 = Red channel select

01 = Green channel select

10 = Blue channel select

11 = Reserved

Software

Reset

Any write to Software Reset causes all cells to be reset. It is recommended

that a software reset be performed after a power-up before any other register

writes.

Auto-cycle

Reset

Any write to Auto-cycle Reset causes the auto-cycle counter to reset

to RINP. This function is only required when LINEBYLINE = 1.

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