AD9444-CMOSSLASHPCB datasheet(25/41 Pages) AD

25 / 41 page

AD9444

Rev. 0 | Page 24 of 40

Table 10. Digital Output Coding

Code

VIN+ − VIN−

Input Span = 2 V p-p (V)

VIN+ − VIN−

Input Span = 1 V p-p (V)

Digital Output

Offset Binary (D9••••••D0)

Digital Output

Twos Complement (D9••••••D0)

16383

1.000

0.500

11 1111 1111 1111

01 1111 1111 1111

8192

10 0000 0000 0000

00 0000 0000 0000

8191

−0.000122

−0.000061

01 1111 1111 1111

11 1111 1111 1111

−1.00

−0.5000

00 0000 0000 0000

10 0000 0000 0000

EVALUATION BOARD

Evaluation boards are offered to configure the AD9444 in

either CMOS or LVDS mode. Each represents a recommended

configuration for using the device over a wide range of sample

rates and analog input frequencies. These evaluation boards

provide all the support circuitry required to operate the ADC in

its various modes and configurations. Complete schematics and

layout plots follow and demonstrate the proper routing and

grounding techniques that should be applied at the system level.

It is critical that signal sources with very low phase noise

(< 1 ps rms jitter) be used to realize the ultimate performance

of the converter. Proper filtering of the input signal, to remove

harmonics and lower the integrated noise at the input, is also

necessary to achieve the specified noise performance.

The evaluation boards are shipped with an ac to 6 V dc power

supply. The evaluation boards include low dropout regulators to

generate the various dc supplies required by the AD9444 and its

support circuitry. Separate power supplies are provided to iso-

late the DUT from the support circuitry. Each input configura-

tion can be selected by proper connection of various jumpers

(see Figure 47 to Figure 50 and Figure 59 to Figure 61).

Both the LVDS and CMOS versions of the evaluation board are

compatible with the high speed ADC FIFO evaluation kit (part

number HSC-ADC-EVALA-SC). The kit includes a high speed

data capture board that provides a hardware solution for captur-

ing up to 32Ksamples of high speed ADC output data in a FIFO

memory chip (user upgradeable to 256K samples). Software is

provided to enable the user to download the captured data to a

PC via the USB port. This software also includes a behavioral

model of the AD9444 and many other high speed ADCs.

Behavioral modeling of the AD9444 is also available at

www.analog.com/ADIsimADC. The ADIsimADC™ software

supports virtual ADC evaluation using ADI proprietary

behavioral modeling technology. This allows rapid comparison

between the AD9444 and other high speed ADCs, with or

without hardware evaluation boards.

The AD9444 LVDS evaluation board includes an on-board,

LVDS-to-CMOS translator, but the user may choose to remove

the translator and terminations to access the LVDS outputs

directly.

The CMOS evaluation board includes a buffer for the output

data and the DCO output clock of the AD9444.

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