AD9444-CMOSSLASHPCB datasheet(21/41 Pages) AD

21 / 41 page

AD9444

Rev. 0 | Page 20 of 40

THEORY OF OPERATION

The AD9444 architecture is optimized for high speed and ease

of use. The analog inputs drive an integrated, high bandwidth,

track-and-hold circuit that samples the signal prior to quantiza-

tion by the 14-bit pipeline ADC core. The device includes an

on-board reference and input logic that accepts TTL, CMOS, or

LVPECL levels. The digital output logic levels are user selectable

as standard 3 V CMOS or LVDS (ANSI-644 compatible) via the

OUTPUT MODE pin.

ANALOG INPUT AND REFERENCE OVERVIEW

A stable and accurate 0.5 V voltage reference is built into the

AD9444. The input range can be adjusted by varying the refer-

ence voltage applied to the AD9444, using either the internal

reference or an externally applied reference voltage. The input

span of the ADC tracks reference voltage changes linearly. The

various reference modes are described in the next few sections.

Internal Reference Connection

A comparator within the AD9444 detects the potential at the

SENSE pin and configures the reference into four possible

states, which are summarized in Table 9. If SENSE is grounded,

the reference amplifier switch is connected to the internal resis-

tor divider (see Figure 40), setting VREF to ~1 V. Connecting

the SENSE pin to VREF switches the reference amplifier output

to the SENSE pin, completing the loop and providing a ~0.5 V

reference output. If a resistor divider is connected, as shown in

Figure 41, the switch again sets to the SENSE pin. This puts the

reference amplifier in a noninverting mode with the VREF

output defined as

⎟

⎠

⎞

⎜

⎝

⎛ +

VREF

0.5

In all reference configurations, REFT and REFB drive the A/D

conversion core and establish its input span. The input range of

the ADC always equals twice the voltage at the reference pin for

either an internal or an external reference.

Internal Reference Trim

The internal reference voltage is trimmed during the produc-

tion test to adjust the gain (analog input voltage range) of the

AD9444. Therefore, there is little advantage to the user supply-

ing an external voltage reference to the AD9444. The gain trim

is performed with the AD9444’s input range set to 2 V p-p

nominal (SENSE connected to AGND). Because of this trim,

and because the 2 V p-p analog input range provides maximum

ac performance, there is little benefit to using analog input

ranges < 2 V p-p. Users are cautioned that the differential

nonlinearity of the ADC varies with the reference voltage.

Configurations that use < 2 V p-p may exhibit missing codes

and, therefore, degraded noise and distortion performance.

µF

0.1

µF

VREF

SENSE

0.5V

AD9444

VIN–

VIN+

REFT

0.1

µF

0.1

µF

0.1

µF

REFB

SELECT

LOGIC

ADC

CORE

Figure 40. Internal Reference Configuration

µF

0.1

µF

VREF

SENSE

0.5V

AD9444

VIN–

VIN+

REFT

0.1

µF

0.1

µF

0.1

µF

REFB

SELECT

LOGIC

ADC

CORE

Figure 41. Programmable Reference Configuration

AD9444-CMOS/PCB データシート(PDF) 21 Page - Analog Devices

AD9444-CMOS/PCB データシート(HTML) 21 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41

データシートダウンロード

リンク URL

AD9444-CMOS/PCB データシート(PDF) 21 Page - Analog Devices

AD9444-CMOS/PCB データシート(HTML) 21 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41

データシート ダウンロード

リンク URL

データシートダウンロード