AD9444-CMOSSLASHPCB datasheet(7/41 Pages) AD

7 / 41 page

AD9444

Rev. 0 | Page 6 of 40

SWITCHING SPECIFICATIONS

AVDD1 = 3.3 V, AVDD2 = 5.0 V, DRVDD = 3.3 V, unless otherwise noted.

Table 4.

AD9444BSVZ-80

Parameter

Temp

Test Level

Min

Typ

Max

Unit

CLOCK INPUT PARAMETERS

Maximum Conversion Rate

Full

MSPS

Minimum Conversion Rate

Full

MSPS

CLK Period

Full

12.5

CLK Pulse Width High1 (tCLKH)

Full

CLK Pulse Width Low1 (tCLKL)

Full

DATA OUTPUT PARAMETERS

Output Propagation Delay—CMOS (tPD)2 (DX, DCO+)

Full

5.25

Output Propagation Delay—LVDS (tPD)3 (DX+, DCO+)

Full

7.5

Pipeline Delay (Latency)

Full

Cycles

Aperture Delay (tA)

Full

Aperture Uncertainty (Jitter, tJ)

Full

0.2

ps rms

1 With duty cycle stabilizer (DCS) enabled.

2 Output propagation delay is measured from clock 50% transition to data 50% transition, with 5 pF load.

3 LVDS RTERM = 100 Ω. Measured from the 50% point of the rising edge of CLK+ to the 50% point of the data transition.

N–12

N–11

N+1

AIN

CLK+

CLK–

DATA OUT

DCO+

DCO–

N+1

N–1

CLKH

CLKL

12 CLOCK CYCLES

CPD

Figure 2. LVDS Mode Timing Diagram

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