AD9444-CMOSSLASHPCB datasheet(14/41 Pages) AD

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AD9444

Rev. 0 | Page 13 of 40

Table 8. Pin Function Descriptions—100-Lead TQFP/EP in CMOS Mode

Pin No.

Mnemonic

Description

1, 8 to 9, 16 to 18,

24 to 27, 34 to 35,

38, 41 to 42, 87,

89 to 95, 98

AVDD1

3.3 V (±5%) Analog Supply.

2 to 4, 7,

43 to 46, 49 to 52,

55 to 60, 65

DNC

Do Not Connect. These

pins should float.

OUTPUT

MODE

CMOS Compatible Output

Logic Mode Control Pin.

OUTPUT MODE = 0 for CMOS

mode, and OUTPUT MODE =

1 (AVDD1) for LVDS outputs.

DFS

Data Format Select Pin.

CMOS control pin that de-

termines the format of the

output data. DFS = high

(AVDD1) for twos comple-

ment, DFS = low (ground) for

offset binary format.

SENSE

Reference Mode Selection.

Connect to AGND for internal

1 V reference, and connect to

AVDD2 for external reference.

VREF

1.0 V Reference I/O—

Function Dependent on

SENSE. Decouple to ground

with 0.1 µF and 10 µF

capacitors.

12, 15, 20, 23,

32, 86, 88, 96 to

97, 99, Exposed

Heat Sink

AGND

Analog Ground. The exposed

heat sink on the bottom of

the package must be

connected to AGND.

REFT

Differential Reference Out-

put. Decoupled to ground

with 0.1 µF capacitor and to

REFB (Pin 14) with 0.1 µF and

10 µF capacitors.

REFB

Differential Reference Out-

put. Decoupled to ground

with a 0.1 µF capacitor and to

REFT (Pin 13) with 0.1 µF and

10 µF capacitors.

19, 28 to 31,

39 to 40

AVDD2

5.0 V Analog Supply (±5%).

VIN+

Analog Input—True.

VIN−

Analog Input—Complement.

Pin No.

Mnemonic

Description

Internal Bypass Node.

Connect a 0.1 µF capacitor

from this pin to AGND.

CLK+

Clock Input—True.

CLK−

Clock Input—Complement.

47, 54, 62,

75, 83

DRVDD

3.3 V Digital Output

Supply (2.5V to 3.6 V).

48, 53, 61,

67, 74, 82

DRGND

Digital Ground.

DCO−

Data Clock Output—

Complement (CMOS Levels).

DCO+

Data Clock Output—

True.

D0 (LSB)

D0 Output Bit (LSB)

(CMOS Levels).

D1 Output Bit.

D2 Output Bit.

D3 Output Bit.

D4 Output Bit.

D5 Output Bit.

D6 Output Bit.

D7 Output Bit.

D8 Output Bit.

D9 Output Bit.

D10

D10 Output Bit.

D11

D11 Output Bit.

D12

D12 Output Bit.

D13 (MSB)

D13 Output Bit.

Out-of-Range Output.

100

DCS MODE

Clock Duty Cycle Stabilizer

(DCS) Control Pin, CMOS-

Compatible. DCS = low

(AGND) to enable DCS

(recommended). DCS =

high (AVDD1) to disable DCS.

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