STV3550 datasheet(79/144 Pages) STMICROELECTRONICS

79 / 144 page

CPU and System Management Functional Description

STV3550

79/144

When the board is dedicated to low-cost solutions, only one SDRAM (SDRAM 2) is soldered and

the STV3550 Memory Interface is configured by software to only use one SDRAM.

When the board is dedicated to high-end solutions, both SDRAMs are soldered and the STV3550

Memory Interface is configured by software to use both SDRAMs.

Byte Enable signals are provided as described in previous sections, depending on the memory

configuration.

Note:

It is recommended to maintain coherency between hardware and software configurations. It is

especially recommended NOT to use a board equipped with two SDRAMs while the STV3550

Memory Interface is configured in a low-cost configuration as this may create bus contention.

The STV3550 Memory Interface includes an address translator which preventsany external

modification the address bus towards the SDRAMs. Since the data word size differs from one

configuration to the other one, addresses ADDR[11:0] are used in low-cost configurations, while

addresses ADDR[12:1] are used in high-end configurations.

The Address bus is connected as in a low-cost configuration, while the address translator translates

internal addresses ADDR[12:1] on external addresses ADDR[11:0] when a high-end configuration

is required.

Note:

Address translation only concerns addresses ADDR[11:0] and is only performed when the SDRAM

is accessed. Addresses are not translated when the Flash memory is accessed.

STV3550 データシート(PDF) 79 Page - STMicroelectronics