STV3550 datasheet(82/144 Pages) STMICROELECTRONICS

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STV3550

CPU and System Management Functional Description

An external Hard Reset is triggered by asserting a low state on the NRESET pin of the STV3550.

Assertion and de-assertion are considered as asynchronous events.

On a Power-On Reset (POR), the entire STV3550 is reset and the application is rebooted. All

internal states are lost.

The reset is internally delayed by the Build-Up Counter (BUC) in order to wait for oscillator

stabilization as well as to filter any glitches on the NRESET pin. The BUC then generates an

asynchronous internal reset that is propagated to all blocks.

The asynchronous internal reset stops all the clocks that are not needed to boot the STV3550, while

the system clock (for ST20 C2C200 CPU core, STV3550 Memory Interface, STBus Interconnect,

etc.) is switched on the 27 MHz oscillator.

6.4.2

Internal Reset Generated by the Watchdog

When the Watchdog down-counter underflows, the Watchdog triggers a reset. During this reset, the

Real Time Clock is partially reset (compare values are lost), but the time counter is not affected.

Then the reset pulse acts as a reset caused by a POR for all other blocks.

Watchdog resets are flagged in the system in order to apply specific recovery algorithms.

6.4.3

Internal Soft Reset

Each block embeds an internal reset that is controlled by software. This reset behaves as a local

hardware reset and is dedicated for software development step only.

6.5

Booting the STV3550

6.5.1

Typical Boot Sequence

A typical boot sequence aims at configuring all the hardware resources of the STV3550 prior to

executing the main application program that manages the TV chassis.

The STV3550 always boots on the Flash device at address 0x7FFFFFFF. The STV3550 Memory

Interface default configuration complies with most of the devices available on the Flash market, so

the ST20 C2C200 CPU core is able to execute the first application tasks, which are:

●

to speed-up the system clock from 27 MHz to the standard operating frequency by configuring

the STV3550 Clock Generator,

●

to configure the STV3550 Memory Interface to speed-up the Flash accesses and speed-up the

software execution,

●

to configure the STV3550 Memory Interface according to the specifications of the SDRAM

device connected to the STV3550,

●

to activate the instruction and data-cache capabilities of the ST20 C2C200 CPU.

Most applications require the activation of Watchdog capabilities as early as possible, so that this

task can be part of the boot sequence as well.

The STV3550 Memory Interface must be configured in order to be able to access the SDRAM and

execute the main application program. Otherwise, the internal 8-kB SRAM of the ST20 C2C200

CPU is large enough in order to execute the boot sequence which has a low complexity.

Note:

The STV3550 Memory Interface should be configured only once, and it is the responsibility of the

user to keep the STV3550 Memory Interface configuration unchanged in the main application

program.

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