© 2016 Semiconductor Components Industries, LLC

www.onsemi.com

FDMF5821 • Rev. 1.0

3

Pin Configuration

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

8

7

6

5

4

3

2

1

SW

SW

SW

GL

PGND

PVCC

TMON

EN/

FAULT#

PGND

PGND

PGND

PGND

VIN

VIN

VIN

8

7

6

5

4

3

2

1

16

17

18

19

20

21

22

23

32

AGND

33

GL

Figure 3.

Pin Configuration - Top View and Transparent View

Pin Definitions

Pin #

Name

Description

1

PWM

PWM input to the gate driver IC

2

ZCD#

Enable input for the ZCD (Auto DCM) comparator

3

VCC

Power supply input for all analog control functions; this is the

4, 32

AGND

Analog ground for analog portions of the IC and for substrate, internally tied to PGND

5

BOOT

Supply for the high-side MOSFET gate driver. A capacitor from BOOT to PHASE supplies

the charge to turn on the N-channel high-side MOSFET

6

NC

No connect

7

PHASE

Return connection for the boot capacitor, internally tied to SW node

8~11

VIN

Power input for the power stage

12~15, 28

PGND

Power return for the power stage

16~26

SW

Switching node junction between high-side and low-side MOSFETs; also input to the gate

driver SW node comparator and input into the ZCD comparator

27, 33

GL

Gate Low, Low-side MOSFET gate monitor

29

PVCC

Power supply input for LS

(1) gate driver and boot diode

30

TMON

Temperature monitoring & reporting / programmable thermal shutdown pin

31

EN /

FAULT#

Dual-functionality: enable input to the gate driver IC; FAULT# - internal pull-down

physically pulls this pin LOW upon detection of fault condition (HS

(2) MOSFET short or

TMON signal exceeding 1.5 V)

Notes:

1.

LS = Low Side.

2.

HS = High Side.