FDMF5821 datasheet(19/26 Pages) ONSEMI

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FDMF5821 • Rev. 1.0

Application Information

Decoupling Capacitor for PVCC & VCC

For the supply inputs (PVCC and VCC pins), local

decoupling capacitors are required to supply the peak

driving current and to reduce noise during switching

operation. Use at least 0.68 ~ 1 µF / 0402 ~ 0603 / X5R

~ X7R multi-layer ceramic capacitors for both power

rails. Keep these capacitors close to the PVCC and

VCC pins and PGND and AGND copper planes. If they

need to be located on the bottom side of board, put

through-hole vias on each pads of the decoupling

capacitors to connect the capacitor pads on bottom with

PVCC and VCC pins on top.

The supply voltage range on PVCC and VCC is 4.5 V ~

5.5 V, typically 5 V for normal applications.

R-C Filter on VCC

The PVCC pin provides power to the gate drive of the

high-side and low-side power MOSFETs. In most cases,

PVCC can be connected directly to VCC, which is the

pin that provides power to the analog and logic blocks of

the driver. To avoid switching noise injection from PVCC

into VCC, a filter resistor can be inserted between

PVCC and VCC decoupling capacitors.

Recommended filter resistor value range is 0 ~ 10

Ω,

typically 0

Ω for most applications.

Bootstrap Circuit

The bootstrap circuit uses a charge storage capacitor

(CBOOT). A bootstrap capacitor of 0.1 ~ 0.22 µF / 0402 ~

0603 / X5R ~ X7R is usually appropriate for most

switching applications. A series bootstrap resistor may

be needed for specific applications to lower high-side

MOSFET switching speed. The boot resistor is required

when the SPS is switching above 15 V VIN; when it is

effective at controlling VSW overshoot. RBOOT value from

zero to 6

Ω is typically recommended to reduce

excessive voltage spike and ringing on the SW node. A

higher RBOOT value can cause lower efficiency due to

high switching loss of high-side MOSFET.

Do not add a capacitor or resistor between the BOOT

pin and GND.

EN / FAULT# (Input / Output)

The driver in SPS is enabled by pulling the EN pin

HIGH. The EN pin has internal 250 k

Ω pull-down

resistor, so it needs to be pulled-up to VCC with an

external resistor or connected to the controller or system

to follow up the command from them. If the EN pin is

floated, it cannot turn on the driver.

The fault flag LOW signal is asserted on the EN /

FAULT# pin when the driver temperature reaches P-

THDN temperature or a high-side MOSFET fault occurs.

Then the driver shuts down.

The typical pull-up resistor value on EN ~ VCC is 10 k

Ω.

Do not add a noise filter capacitor on the EN pin.

PWM (Input)

The PWM pin recognizes three different logic levels

from PWM controller: HIGH, LOW, and 3-state. When

the PWM pin receives a HIGH command, the gate

driver turns on the high-side MOSFET. When the PWM

pin receives a LOW command, the gate driver turns on

the low-side MOSFET. When the PWM pin receives a

voltage signal inside of the 3-state window (VTRI_Window)

and exceeds the 3-state hold-off time, the gate driver

turns off both high-side and low-side MOSFETs. To

recognize the high-impedance 3-state signal from the

controller, the PWM pin has an internal resistor divider

from VCC to PWM to AGND. The resistor divider sets

a voltage level on the PWM pin inside the 3-state

window when the PWM signal from the controller is

high-impedance.

ZCD# (Input)

When the ZCD# pin sets HIGH, the ZCD function is

disabled and high-side and low-side MOSFETs switch in

CCM (or FCCM, Forced CCM) by PWM signal. When

the ZCD# pin is LOW, the low-side MOSFET turns off

when the SPS driver detects negative inductor current

during the low-side MOSFET turn-on period. This ZCD

feature allows higher converter efficiency under light-

load condition and PFM / DCM operation.

The ZCD# pin has an internal current source from VCC,

so it may not need an external pull-up resistor. Once

VCC is supplied and the driver is enabled, the ZCD# pin

holds logic HIGH without external components and the

driver operates switching in CCM or FCCM. The ZCD#

pin can be grounded for automatic diode emulation in

DCM by the SPS itself, or it can be connected to the

controller or system to follow the command from them.

The typical pull-up resistor value on ZCD# ~ VCC is

10 k

Ω for stable ZCD# HIGH level. If not using the ZCD

feature, tie the ZCD# pin to VCC with a pull-up resistor.

Do not add any noise filter capacitor on the ZCD# pin.

TMON (Output) / P-THDN

During normal operation (no fault detected), the TMON

pin sources an analog current proportional to the

absolute temperature of the gate driver. With 25 k

RTMON and 0.1 µF CTMON on TMON pin to AGND, it

outputs 1 V at 25°C driver TJ and 1.5 V at 150°C driver

TJ. The CTMON is a filter capacitor to minimize switching

noise injection onto the TMON pin. The TMON pin can

be connected to a PWM controller or system controller

and used to monitor the SPS module temperature.

If the TMON pin voltage exceeds 1.5 V with 25 k

RTMON, the driver temperature is over 150°C and the

driver is shut down by the P-THDN feature. The 150°C

thermal shutdown temperature can be adjusted by the

RTMON value to define the THDN temperature for the

application. Refer to the P-THDN section to define

thermal shutdown temperature and RTMON value.

If not using the TMON / P-THDN features, tie the TMON

pin to GND.

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