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FDMF5821 データシート(PDF) 13 Page - ON Semiconductor

部品番号 FDMF5821
部品情報  Smart Power Stage (SPS) Module with Integrated Temperature Monitor
PDF  26 Pages
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メーカー  ONSEMI [ON Semiconductor]
ホームページ  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

FDMF5821 データシート(HTML) 13 Page - ON Semiconductor

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© 2016 Semiconductor Components Industries, LLC
www.onsemi.com
FDMF5821 • Rev. 1.0
12
PWM
GL
GH-PHASE
(internal)
BOOT-GND
VIH_PWM
VIL_PWM
90%
10%
tFALL_GH
tRISE_GL
SW
tPD_PHGLL
tPD_PLGHL
tD_DEADOFF
tD_DEADON
tFALL_GL
tRISE_GH
90%
10%
90%
10%
90%
10%
tPD_PHGLL = PWM HI to GL LO, VIH_PWM to 90% GL
tFALL_GL = 90% GL to 10% GL
tD_DEADON = LS Off to HS On Dead Time, 10% GL to VBOOT-GND <= PVCC - VF_DBOOT - 1V or BOOT-GND dip start point
tRISE_GH = 10% GH to 90% GH, VBOOT-GND <= PVCC - VF_DBOOT - 1V or BOOT-GND dip start point to GL bounce start point
tPD_PLGHL = PWM LO to GH LO, VIL_PWM to 90% GH or BOOT-GND decrease start point, tPD_PLGLH - tD_DEADOFF - tFALL_GH
tFALL_GH = 90% GH to 10% GH, BOOT-GND decrease start point to 90% VSW or GL dip start point
tD_DEADOFF = HS Off to LS On Dead Time, 90% VSW or GL dip start point to 10% GL
tRISE_GL = 10% GL to 90% GL
tPD_PLGLH = PWM LO to GL HI, VIL_PWM to 10% GL
tPD_PLGLH
PVCC - VF_DBOOT - 1V
90%
Figure 27.
PWM Timing Diagram
VIH_PWM
VTRI_HI
(9)
VTRI_LO
VIL_PWM
(12)
3-State
Window
3-State
Window
VIH_PWM
(11)
VTRI_HI
VTRI_LO
(10)
VIL_PWM
PWM
GH-PHASE
GL
(7)
(8)
(8)
(7)
Figure 28.
PWM Threshold Definition
Notes:
7.
The timing diagram in Figure 28 assumes very slow ramp on PWM.
8.
Slow ramp of PWM implies the PWM signal remains within the 3-state window for a time >>> tD_HOLD-OFF.
9.
VTRI_HI = PWM trip level to enter 3-state on PWM falling edge.
10. VTRI_LO = PWM trip level to enter 3-state on PWM rising edge.
11. VIH_PWM = PWM trip level to exit 3-state on PWM rising edge and enter the PWM HIGH logic state.
12. VIL_PWM = PWM trip level to exit 3-state on PWM falling edge and enter the PWM LOW logic state.



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