FDMF5821 datasheet(16/26 Pages) ONSEMI

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FDMF5821 • Rev. 1.0

Exiting 3-State with Low BOOT-SW Voltage

The SPS module is used in multi-phase VR topologies

requiring the module to wait in 3-state condition for an

indefinite time. These long idle times can bleed the boot

capacitor down until eventual clamping occurs based

on PVCC and VOUT. Low BOOT-SW can cause

increased propagation delays in the level-shift circuit as

well as all HDRV floating circuitry, which is biased from

the BOOT-SW rail. Another issue with a depleted

BOOT-SW capacitor voltage is the voltage applied to

the HS MOSFET gate during turn-on. A low BOOT-SW

voltage results in a very weak HS gate drive, hence,

much

larger

RDS(ON) and increased risk for

unreliable operation since the HS MOSFET may not

turn-on if BOOT-SW falls too low.

To address this issue, the SPS monitors for a low

BOOT-SW voltage when the module is in 3-state

condition. When the module exits 3-state condition with

a low BOOT-SW voltage, a 100 ns minimum GL on

time is output regardless of the PWM input. This

ensures the boot capacitor is adequately charged to a

safe operating level and has minimal impact on

transient response of the system. Scenarios of exiting

3-state condition are listed below.

 If the part exits 3-state with a low BOOT-SW voltage

condition and the controller commands PWM=HIGH,

the SPS outputs a 100 ns GL pulse and follows the

PWM=HIGH command (see Figure 30).

 If the part exits 3-state with a low BOOT-SW

voltage condition and the controller commands

PWM=LOW for 100 ns or more, the SPS follows

the PWM input. If PWM=LOW for less than 100 ns,

GL remains on for 100 ns then follows the PWM

input (see Figure 31 and Figure 32).

 If no low BOOT-SW condition is detected, the SPS

follows the PWM command when exiting 3-state

(see Figure 33).

The SPS momentarily stays in an adaptive dead time

mode when exiting 3-state condition or at initial power-

up. This adaptive dead time mode lasts for no more

than two (2) consecutive switching cycles, giving the

boot capacitor ample time to recharge to a safe level.

The module switches back to fixed dead time control for

maximum efficiency.

Low BOOT-SW voltage detected

PWM

GH to

PHASE

LOW

BOOT-SW

detect

GL / GH

off

VIH_PWM

100 ns

GL pulse

Figure 30.

Low BOOT-SW Voltage Detected and

PWM from 3-State to HIGH

GL / GH

off

PWM LOW

> 100 ns

GL pulse

VIL_PWM

PWM

GH to

PHASE

LOW

BOOT-SW

detect

Low BOOT-SW voltage detected

Figure 31.

Low BOOT-SW Voltage Detected and

PWM from 3-State to LOW for more than 100 ns

GL / GH

off

PWM LOW

< 100 ns

100 ns

GL pulse

VIL_PWM

PWM

GH to

PHASE

LOW

BOOT-SW

detect

Low BOOT-SW voltage detected

Figure 32.

Low BOOT-SW voltage Detected and

PWM from 3-State to LOW for Less than 100 ns

GH to

PHASE

GL / GH

off

Low BOOT-SW voltage NOT detected

LOW

BOOT-SW

detect

GL / GH

off

VIH_PWM

PWM

VIL_PWM

Figure 33.

Low BOOT-SW Voltage NOT Detected

and PWM from 3-State to HIGH or LOW

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