FDMF5821 datasheet(17/26 Pages) ONSEMI

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FDMF5821 • Rev. 1.0

Zero Cross Detect (ZCD) Operation

The ZCD control block houses the circuitry that

determines when the inductor current reverses direction

and controls when to turn off the low-side MOSFET. A

low offset comparator monitors

the SW-to-PGND

voltage of the low-side MOSFET during the LS

MOSFET on-time. When the sensed voltage switches

polarity from negative to positive, the comparator

changes state and reverse current has been detected.

This comparator offset must sense the negative VSW

within a 0.5 mV worst-case range. The negative offset

is to ensure the inductor current never reverses; some

small body-diode conduction is preferable to having

negative current.

The comparator is switched on after the rising edge of

the low-side gate drive and turned off by the signal at

the input to the low-side gate driver. In this way, the

zero-current comparator is connected with a break-

before-make connection, allowing the comparator to be

designed with low-voltage transistors.

PWM

ZCD#

GH to

Inductor

Current

(simplified

slopes)

(zoom)

VIH_ZCD#

tPD_PHGLL

VIL_ZCD#

VIH_PWM

VIL_PWM

10%

90%

10%

tD_DEADON

tPD_PLGHL

tD_DEADOFF

tPD_PHGLL

tD_DEADON2

tPD_ZCD

10%

90%

tPD_PHGHH

10%

Delay from PWM going

HIGH to HS VGS HIGH

(HS turn-on in DCM)

90%

10%

90%

tPD_ZHGLH

tPD_ZLGLL

Delay from ZCD# going

HIGH to LS VGS HIGH

Delay from ZCD# going

LOW to LS VGS LOW

VIN

VOUT

CCM

(Negative inductor current)

DCM

CCM operation with

positive inductor current

CCM operation with

negative inductor current

DCM operation: Diode

Emulation using the GL (LS

MOSFET VGS) to eliminate

negative inductor current

DCM operation: Diode

Emulation using the GL (LS

MOSFET VGS) to eliminate

negative inductor current

ZCD# used to

control negative

inductor current

(fault condition)

VZCD_OFF :

-0.5mV

Figure 34.

ZCD# & PWM Timing Diagram

Temperature Monitor (TMON)

The FDMF5821 provides a temperature monitor (TMON)

to warn of over-temperature conditions. The gate driver

uses the TMON pin to source an analog current

proportional to absolute temperature (PTAT). It is

expected that the analog current will be used with a

properly chosen external resistor to AGND to develop a

voltage across TMON (VTMON) proportional to the

temperature. A filter capacitance may be needed to

minimize noise spikes in the analog current, ITMON. Noise

spikes are generated from power MOSFET switching

dv / dt and di / dt coupling back into the driver VCC pin.

The TMON pin needs a pull-down resistor (RTMON) and

filter capacitor (CTMON) to AGND. With 25 kΩ RTMON and

0.1 µF CTMON, the TMON voltage is around 1 V at 25°C

of gate driver TJ, and 1.5 V when the driver temperature

reaches 150°C. The VTMON signal can be connected to

PWM controller or MCU in system to indicate the

thermal status of the gate driver. Figure 35 shows gate

driver temperature versus TMON pin voltage with 25 k

RTMON and 0.1 µF CTMON.

150

TJ [°C]

1.0

1.45

VTMON

[V]

* RTMON = 25 kW, CTMON = 0.1 µF

Figure 35.

Gate Driver TJ vs. VTMON

The TMON voltage is defined by following equation:

(1)

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