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GD25LE256DFJS データシート(PDF) 29 Page - GigaDevice Semiconductor (Beijing) Inc.

部品番号 GD25LE256DFJS
部品情報  1.8V Uniform Sector Dual and Quad Serial Flash
PDF  83 Pages
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メーカー  GIGADEVICE [GigaDevice Semiconductor (Beijing) Inc.]
ホームページ  http://www.gigadevice.com/
Logo GIGADEVICE - GigaDevice Semiconductor (Beijing) Inc.

GD25LE256DFJS データシート(HTML) 29 Page - GigaDevice Semiconductor (Beijing) Inc.

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1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LE256D
29
7.11. Quad Output Fast Read (6BH)
The Quad Output Fast Read command is followed by 3-byte address (A23-A0) or a 4-byte address (A31-A0) and a
dummy byte, and each bit is latched in on the rising edge of SCLK, then the memory contents are shifted out 4-bit per clock
cycle from IO3, IO2, IO1 and IO0. The command sequence is shown in followed Figure12. The first byte addressed can be
at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out.
The default read mode is 3-byte address mode, and the lower 128Mbit can be read with a single Quad Output Fast Read
(6BH) command. By entering 4-byte address mode, or to set EN4B (S11) bit to 1, the higher 128Mbit can be read with a
single Quad Output Fast Read (6BH) command.
Figure12. Quad Output Fast Read Sequence Diagram
Command
0
1
2
3
4
5
6
7
6BH
CS#
SCLK
SI(IO0)
SO(IO1)
High-Z
8
9 10
28 29 30 31
3
2
1
0
23 22 21
24-bit address
34 35 36 37
33
1
5
1
5
1
5
1
38 39
Byte1
32
42 43 44 45
41
46 47
40
5
Dummy Clocks
0
4
0
4
0
4
0
4
4
5
WP#(IO2)
High-Z
HOLD#(IO3)
High-Z
CS#
SCLK
SI(IO0)
SO(IO1)
WP#(IO2)
HOLD#(IO3)
2
6
2
6
2
6
2
6
6
3
7
3
7
3
7
3
7
7
Byte2 Byte3 Byte4
Note: The device default is in 24-bit address mode. For 4-byte mode, the address length becomes 32-bit.



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