| データシートサーチシステム |
|
GD25LE256DFJS データシート(PDF) 30 Page - GigaDevice Semiconductor (Beijing) Inc. |
|
|
|||||||||||||||||||||||||||||
GD25LE256DFJS データシート(HTML) 30 Page - GigaDevice Semiconductor (Beijing) Inc. |
|
30 / 83 page ![]() 1.8V Uniform Sector Dual and Quad Serial Flash GD25LE256D 30 7.12. Dual I/O Fast Read (BBH) The Dual I/O Fast Read command is similar to the Dual Output Fast Read command but with the capability to input the 3-byte address (A23-0) or a 4-byte address (A31-A0) and a “Continuous Read Mode” byte 2-bit per clock by SI and SO, and each bit is latched in on the rising edge of SCLK, then the memory contents are shifted out 2-bit per clock cycle from SI and SO. The command sequence is shown in followed Figure13. The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. The default read mode is 3-byte address mode, and the lower 128Mbit can be read with a single Dual I/O Fast Read (BBH) command. By entering 4-byte address mode, or to set EN4B (S11) bit to 1, the higher 128Mbit can be read with a single Dual I/O Fast Read (BBH) command. Dual I/O Fast Read with “Continuous Read Mode” The Dual I/O Fast Read command can further reduce command overhead through setting the “Continuous Read Mode” bits (M7-0) after the input 3-byte address (A23-A0) or a 4-byte address (A31-A0). If the “Continuous Read Mode” bits (M5- 4) = (1, 0), then the next Dual I/O Fast Read command (after CS# is raised and then lowered) does not require the BBH command code. The command sequence is shown in followed Figure13a. If the “Continuous Read Mode” bits (M5-4) do not equal (1, 0), the next command requires the first BBH command code, thus returning to normal operation. Figure13. Dual I/O Fast Read Sequence Diagram (M5-4 ≠ (1, 0)) Command 0 1 2 3 4 5 6 7 BBH CS# SCLK SI(IO0) SO(IO1) 8 9 10 11 12 13 14 15 6 4 2 0 6 4 2 0 16 17 18 19 20 21 22 23 6 4 2 0 6 4 2 0 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 A23-16 A15-8 A7-0 M7-0 CS# 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 SI(IO0) SO(IO1) 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 SCLK 6 7 Byte1 Byte2 Byte3 Byte4 Note: The device default is in 24-bit address mode. For 4-byte mode, the address length becomes 32-bit. |
|
リンク URL |
| ALLDATASHEETはお客様のビジネスに役立ちますか? [ DONATE ] |
Alldatasheetは | 広告 | お問い合わせ | プライバシーポリシー | データシートへのリンク | リンク交換 | メーカーリスト All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |