GD25LE256DFJS datasheet(12/83 Pages) GIGADEVICE

12 / 83 page

1.8V Uniform Sector

Dual and Quad Serial Flash

GD25LE256D

NOTE:

1. When SRP1, SRP0= (1, 0), a Power-Down, Power-Up cycle will change SRP1, SRP0 to (0, 0) state.

2. This feature is available on special order. Please contact GigaDevice for details.

QE bit.

The Quad Enable (QE) bit is a non-volatile Read/Write bit in the Status Register that allows Quad operation. When

the QE bit is set to 0 (Default) the WP# pin and HOLD# pin are enable. When the QE pin is set to 1, the Quad IO2 and IO3

pins are enabled. (It is best to set the QE bit to 0 to avoid short issue if the WP# or HOLD# pin is tied directly to the power

supply or ground)

LB2, LB3 bits

The LB2, LB3 bits are non-volatile One Time Program (OTP) bits in Status Register (S12-S13) that provide the write

protect control and status to the Security Registers. The default state of LB2-LB3 are 0, the security registers are unlocked.

The LB2-LB3 bits can be set to 1 individually using the Write Register instruction. The LB2-LB3 bits are One Time

Programmable, once they are set to 1, the Security Registers will become read-only permanently.

CMP bit

The CMP bit is a non-volatile Read/Write bit in the Status Register (S14). It is used in conjunction with the BP4-BP0

bits to provide more flexibility for the array protection. Please see the Status registers Memory Protection table for details.

The default setting is CMP=0.

SUS1, SUS2 bit

The SUS1 and SUS2 bits are read only bit in the status register (S15 and S10) that are set to 1 after executing an

Erase/Program Suspend (75H) command (The Erase Suspend will set the SUS1 to 1,and the Program Suspend will set the

SUS2 to 1). The SUS1 and SUS2 bit are cleared to 0 by Erase/Program Resume (7AH) command, software reset (66H+99H)

command as well as a power-down, power-up cycle.

EN4B bit

The EN4B bit is a volatile Read/Write bit in the status register (S11) that is set to 1 after executing the Enable 4-byte

Mode command, and cleared to 0 (default ) by the Disable 4-byte Mode command as well as a power-down, power-up cycle.

GD25LE256DFJS データシート(PDF) 12 Page - GigaDevice Semiconductor (Beijing) Inc.