STM8S datasheet(216/467 Pages) STMICROELECTRONICS

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16-bit advanced control timer (TIM1)

RM0016

216/467

DocID14587 Rev 14

Note:

As the bits AOE, BKP, BKE, OSSR, and OSSI can be write-locked depending on the LOCK

configuration, it is necessary to configure all of them during the first write access to the

TIM1_BKR register.

Bit 3 OSSR: Off state selection for Run mode

This bit is used when MOE = 1 on channels with a complementary output which are configured as

outputs. See OC/OCN enable description for more details (Section 17.7.13).

0: When inactive, OC/OCN outputs are disabled (OC/OCN enable output signal = 0)

1: When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCiE = 1 or

CCiNE = 1, after which the OC/OCN enable output signal = 1

Note: This bit can no longer be modified while LOCK level 2 has been programmed (LOCK bits in

TIM1_BKR register).

Bit 2 OSSI: Off state selection for idle mode

This bit is used when MOE = 0 on channels configured as outputs. See OC enable description for

more details (Section 17.7.13).

0: When inactive, OCi outputs are disabled (OCi enable output signal = 0)

1: When inactive, OCi outputs are forced first with their idle level as soon as CCiE = 1 (OC enable

output signal = 1)

Note: This bit can no longer be modified while LOCK level 2 has been programmed (LOCK bits in the

TIM1_BKR register).

Bits 1:0 LOCK[1:0]: Lock configuration

These bits offer a write protection against software errors.

00: LOCK off - No bits are write protected

01: LOCK level 1 - OISi bit in TIM1_OISR register and BKE/BKP/AOE bits in TIM1_BKR register can

no longer be written.

10: LOCK level 2 - LOCK level 1 + CC polarity bits (CCiP bits in TIM1_CCERi registers, as long as

the related channel is configured in output through the CCiS bits) as well as the OSSR and OSSI

bits can no longer be written.

11: LOCK Level 3 - LOCK level 2 + CC control bits (OCiM and OCiPE bits in TIM1_CCMRi registers,

as long as the related channel is configured in output through the CCiS bits) can no longer be

written.

Note: The LOCK bits can be written only once after reset. Once the TIM1_BKR register has been

written, their content is frozen until the next reset.

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