AD9546SLASHPCBZ datasheet(119/205 Pages) AD

119 / 205 page

Data Sheet

AD9546

Rev. 0 | Page 119 of 205

SOURCE PROFILES

SOURCE PROFILES OVERVIEW

The source profiles give the user a method to define how an

input source, when selected by a DPLL channel via the active

translation profile, interacts with the DPLL. The user has access

to the 14 source profiles (one profile for each source) via the

address per Table 78. Each source profile gives the user control

of the following parameters:

•

DPLL phase lock detector

•

DPLL frequency lock detector

•

Phase step limit

•

Skew adjustment

•

Initial phase skew refinement steps

Table 78. Source Name vs. Source Profile Address Range

Source Name

Start Address

End Address

REFA

0x0800

0x0811

REFAA

0x0820

0x0831

REFB

0x0840

0x0851

REFBB

0x0860

0x0871

Auxiliary NCO 0

0x0880

0x0891

Auxiliary NCO 1

0x08A0

0x08B1

DPLL0

0x08C0

0x08D1

DPLL1

0x08E0

0x08F1

IUTS 0

0x0900

0x0911

IUTS 1

0x0920

0x0931

Auxiliary REF0

0x0940

0x0951

Auxiliary REF1

0x0960

0x0971

Auxiliary REF2

0x0980

0x0991

Auxiliary REF3

0x09A0

0x09B1

A source profile links to a DPLL translation profile (see the

Translation Profiles section) via Bits[4:0] of the translation

profile register start address shown in Table 74 plus an offset of

1 (decimal). The selected source (per Bits[4:0] in the associated

translation profile) identifies the source name in Table 78.

DPLL PHASE/FREQUENCY LOCK DETECTOR

See the DPLL Lock Detectors section for details concerning the

phase and frequency detectors of the DPLL.

PHASE STEP LIMIT

Although the AD9546 can switch between multiple reference

inputs, some applications use only one input and handle

reference switching externally (see Figure 86). This

arrangement forfeits the ability of the AD9546 to mitigate the

output disturbance associated with a reference switchover,

because the reference switchover is not under the control of the

AD9546. However, the AD9546 offers a phase transient

threshold detection feature to help identify when an external

reference switchover occurs and acts accordingly.

AD9546

REFx

REFERENCE 1

REFERENCE 2

SWITCHOVER

CONTROL

Figure 86. External Reference Switching

Phase transient threshold detection works by monitoring the

output of the DPLL phase detector for phase transients but in a

manner that is somewhat jitter tolerant. Otherwise, the phase

transient threshold detector is prone to false positives.

To control the phase transient detector, use Bits[31:0]

(unsigned) of the appropriate source profile at the start address

shown in Table 78 plus an offset of 10 to 13 (decimal).

Bits[31:0] constitute the phase step threshold value. A phase

step threshold value of zero (default) disables the phase

transient threshold detector, whereas a nonzero value serves to

activate the phase transient threshold detector as well as define

the desired threshold (ΦTHRESH) in units of picoseconds per the

following equation:

ΦTHRESH = Phase Step Threshold × 10−12

(14)

The phase transient threshold detector is not active unless the

DPLL indicates frequency locked status.

Determine the value of the phase step threshold value necessary

for a 12 ns limit (that is, ΦTHRESH = 12 × 10−9). Solving

Equation 14 for phase step threshold yields

Phase Step Threshold = ΦTHRESH/10−12

= (12 × 10−9)/10−12

= 12,000

= 0x 0000 2EE0 (hexadecimal)

To reduce the likelihood of threshold violations induced by

jitter, the user must choose ΦTHRESH to be at least two times the

expected rms jitter (σJITTER) associated with the input reference

signal.

ΦTHRESH ≥ 2 × σJITTER

(15)

As such, in the previous example for a phase step threshold of

12,000, an input signal with 12 ns rms jitter is likely to produce

false positives, because it violates the inequality in Equation 15.

To reduce the likelihood of a false positive, the inequality in

Equation 15 implies that a phase step threshold of 24,000 is a

better choice. However, even with a value of 24,000, there is still

a slight probability of a jitter sample exceeding 2 × σJITTER. As

such, multiplying σJITTER by four to six is an even better choice.

When a phase transient occurs that exceeds the prescribed

value, one or both of the following two events occur, depending

on the state of Bit 7 of Register 0x2105 (for PLL0) and

•

The DPLL initiates a new acquisition sequence

•

The reference monitor is reset

AD9546/PCBZ データシート(PDF) 119 Page - Analog Devices

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