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Data Sheet

AD9546

Rev. 0 | Page 123 of 205

DPLL FEEDBACK DIVIDER (N DIVIDER)

The DPLL feedback N divider consists of user-programmable

integer part and fractional part. The fractional part, however, is

only available in buildout mode (see the Frequency Translation

Loops section).

Rather than offering direct programming control of the

N divider, the AD9546 makes use of translation profiles (see the

Translation Profiles section). Within each translation profile,

the following four control elements are associated with the N

divider:

•

Buildout N divider integer part (N buildout)

•

Hitless N divider integer part (N hitless)

•

Buildout fractional multiplier (FRAC)

•

Buildout fractional modulus (MOD)

N buildout and N hitless are 32-bit, unsigned integers (only

Bits[29:0] are meaningful because Bits[31:30] must be zero).

FRAC and MOD are 24-bit, unsigned integers.

There are 12 occurrences of the four control elements

coinciding with the 12 translation profiles. Table 74 in the

Frequency Translation Loops section shows the address ranges

associated with the 12 translation profiles. Note that there are

constraints on programming the N divider, as described in the

Frequency Translation Loops section.

N Divider for Phase Buildout Mode

In phase buildout mode, the N divider divide ratio consists of

an integer and fractional part, as follows:

N divider divide ratio = (N buildout + 1) + FRAC/MOD

To program the value of N buildout, use Bits[31:0] (unsigned)

of the appropriate translation profile at the start address shown

in Table 74 plus an offset of 12 to 15 (decimal). The programmed

value of N buildout constitutes one less than the desired integer

part of the divide ratio. That is, an N buildout value of 0

constitutes an integer divide ratio of 1. Therefore, N buildout

provides integer divide ratios from 1 to 230 (1,073,741,824).

For example, for an N divider divide ratio 1,000,000,

N buildout = 999,999 (0x 000F 423F hexadecimal).

Note that changing the value of N buildout or MOD in a

currently active translation profile causes the associated DPLL

to reacquire its reference input signal. However, the DPLL can

accommodate on-the-fly changes to the FRAC value without

causing a reacquisition.

When the desired N divider divide ratio requires a fractional

component, the FRAC and MOD control elements are

necessary. To program the value of FRAC, use Bits[23:0]

(unsigned) of the appropriate translation profile at the start

address shown in Table 74 plus an offset of 16 to 18 (decimal).

To program the value of MOD, use Bits[23:0] (unsigned) of the

appropriate translation profile at the start address shown in

Table 74 plus an offset of 19 to 21 (decimal).

For the special case of FRAC = 0, the user must also program

MOD = 0 to ensure proper device functionality. Furthermore,

the value of FRAC must be less than the value of MOD.

For phase buildout applications that require the N divider to be

integer only, program MOD = 0.

For example, suppose the desired fractional part of the N divider

divide ratio is 0.387429. Then, the corresponding fraction is

FRAC/MOD = 387,429/1,000,000. Generally, the user reduces

the fraction, FRAC/MOD, to its lowest terms, but in this

example, the fraction is irreducible. Therefore, FRAC = 387,429

(0x 0005 E965 hexadecimal) and MOD = 1,000,000 (0x 000F

4240 hexadecimal).

N Divider in Internal Zero Delay Mode

When operating in zero delay (hitless) mode, the AD9546

behaves like an Integer N PLL. Thus, the N divider divide ratio

must be an integer (that is, no fractional part). As such, the

AD9546 ignores the FRAC and MOD control elements when

operating in zero delay mode.

Note that zero delay operation makes use of a different integer

part N divider control element than buildout operation. Thus,

zero delay operation requires programming of N hitless rather

than N buildout. To program the value of N hitless, use

Bits[31:0] (unsigned) of the appropriate translation profile at

the start address shown in Table 74 plus an offset of 8 to 11

(decimal). The programmed value of N hitless constitutes one

less than the desired divide ratio. That is, an N hitless value of 0

constitutes an integer divide ratio of 1. Therefore, N hitless

provides integer divide ratios from 1 to 230 (1,073,741,824).

Note that operating in zero delay (hitless) mode still requires

the user to program N buildout to ensure proper operation of

the DPLL loop filter. However, the value of N buildout is not

the same as N hitless. For internal zero delay operation,

N buildout relates to N hitless per the following (rounded to the

nearest integer):

N Buildout = N Hitless × 2 × Q/M

where:

Q is the divide ratio of the Q divider.

M is the divide ratio of the M divider (see Figure 82).

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