AD9546SLASHPCBZ datasheet(121/205 Pages) AD

121 / 205 page

Data Sheet

AD9546

Rev. 0 | Page 121 of 205

Because the feedback path of the DPLL includes the loop filter,

the feedback signal has the benefit of reduced jitter and an

inherent resistance to change (a consequence of the typically

narrow bandwidth of the loop filter). As such, when the

AD9546 switches to a new reference, the phase and frequency

of the old reference tends to persist in the feedback path of the

DPLL. The feedback path persistence provides some time for

the DPLL to compare the new reference signal to the old one.

As shown in Figure 87, the reference likely exhibits jitter. The

presence of jitter implies uncertainty in the measured time offset

between the feedback and reference signals. This uncertainty, in

turn, leads to a potential error in the determination of the

correct phase buildout value in the DPLL.

To help mitigate jitter induced errors in the assessment of the

phase buildout value, the AD9546 provides a phase skew

refinement feature. To activate the phase skew refinement

feature, use Bits[7:0] (unsigned) of the appropriate source

profile at the start address shown in Table 78 plus an offset of

17 (decimal). Bits[7:0] constitute the phase skew refinement

steps value.

A phase skew refinement steps value of zero (default) disables

the phase skew refinement feature. With the phase skew

refinement feature disabled, the phase buildout value is an

unfiltered snapshot of the reference and feedback time offset at a

single sampled edge, which includes the contribution of any jitter

present on the reference signal.

A nonzero phase skew refinement steps value, K, sets the

number of phase samples the AD9546 analyzes as part of the

phase skew refinement process. That is, instead of taking the

first phase sample (jitter included) as the phase buildout value,

the phase skew refinement feature processes the first K phase

samples to assess the reference jitter and to determine the phase

buildout value. As such, the phase skew refinement feature

extends the time required to determine a phase buildout value

following a reference switchover, but the extra time yields a

more accurate phase buildout value.

The phase skew refinement process operates under the

assumption that the feedback and reference clocks are of the same

frequency, or at least very close. If they are not the same

frequency, the frequency offset appears as a linear phase slew,

which quickly becomes the dominant phase contributor and

masks any jitter that may be present on the reference signal.

Therefore, a reference switchover between references of

dissimilar frequency results in degraded performance of the

phase skew refinement feature.

REFERENCE JITTER

FEEDBACK

SIGNAL

REFERENCE

SIGNAL

SUPPRESSED

JITTER

NOMINAL TIME OFFSET BETWEEN OLD REFERENCE SIGNAL FEEDBACK AND NEW REFERENCE SIGNAL

THE OLD REFERENCE SIGNAL TEMPORARILY PERSISTS IN THE FEEDBACK SIGNAL

REFERENCE

SWITCHOVER

UNCERTAINTY

Figure 87. DPLL Reference and Feedback Signals

AD9546/PCBZ データシート(PDF) 121 Page - Analog Devices

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