AD9546SLASHPCBZ datasheet(122/205 Pages) AD

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AD9546

Data Sheet

Rev. 0 | Page 122 of 205

DIGITAL PLL (DPLL)

DPLL OVERVIEW

The DPLL is a completely digital implementation of a PLL.

Figure 88 shows the fundamental building blocks of an APLL

and a DPLL. An APLL typically relies on a VCO as the

frequency element for generating an output signal, where the

output frequency depends on an applied dc voltage. A DPLL,

conversely, uses an NCO, which relies on a digital frequency

tuning word (FTW) to produce the output frequency. A VCO

inherently produces a timing signal because the VCO is, by

definition, an oscillator, whereas the AD9546 NCO requires an

external timing source, the system clock. The fundamental

difference between an APLL and a DPLL is that the VCO in an

APLL can tune to any frequency within its operating

bandwidth, whereas the NCO in a DPLL can only tune to

discrete frequencies (by virtue of the FTW).

PHASE

DETECTOR

DIVIDER

LOOP

FILTER

VCO

ANALOG

PHASE

ERROR

VOLTAGE

FIXED LOOP

BANDWIDTH

APLL

DIGITAL

PHASE

DETECTOR

DIVIDER

DIGITAL

LOOP

FILTER

NUMERIC

PHASE

ERROR

SYSTEM

CLOCK

PROGRAMMABLE

LOOP BANDWIDTH

DPLL

NCO

NUMERIC

COEFFICIENTS

NUMERIC

FREQUENCY

TUNING WORD

Figure 88. APLL vs. DPLL

The DPLLs in the AD9546 have a phase detector (that operates

on numeric time stamps at its reference and feedback inputs

rather than physical clock signals) and a digital loop filter with

programmable bandwidth. The digital loop filter output yields

a digital FTW (instead of a dc voltage, as in the case of an

analog PLL) that produces a corresponding NCO output

frequency.

DPLL LOOP CONTROLLER

The DPLL has several operating modes: freerun, holdover, and

active. To ensure seamless transition between modes, the DPLL

has a loop controller. The loop controller sets the appropriate

DPLL operating mode based on the prevailing requirements of

automatic reference switching or manual control settings.

Switchover

Switchover occurs when the loop controller switches directly

from one input reference to another (see the Reference

Switching section). To handle a reference switchover, the

AD9546 briefly enters holdover mode, loads the DPLL

parameters from the source profile associated with the new

reference, and then immediately recovers.

Holdover or Freerun

Typically, the holdover or freerun state is in effect when all

input references are invalid. However, the user can force the

holdover mode even when one or more references are valid by

programming Bit 1 to Logic 1 of Register 0x2105 (for DPLL0)

or Register 0x2205 (for DPLL1). In holdover mode, the output

frequency remains fixed (to the extent of the stability of the

system clock). The accuracy of the AD9546 in holdover mode

depends on the device programming and availability of the

tuning word history.

To force freerun mode, see the Freerun Tuning Word section.

When the DPLL is in holdover or freerun mode, there is no

active translation profile available (see the Frequency Translation

Loops section). However, the DPLL is still attached to a

translation profile by virtue of Bits[2:0] of Register 0x102A (for

DPLL0) or Register 0x142A (for DPLL1). Bits[2:0] define the

translation profile with a value of x, where x is 0 to 5, that

associates with the DPLL when in holdover or freerun mode.

Because the DPLL attaches to the profile specified by Bits[2:0],

the recommendation is for the user to program Bits[2:0] with

one of the translation profiles the user has configured. For

example, if the user configures Translation Profile 0,

Translation Profile 2, and Translation Profile 5 for use by

DPLL0, program Bits[2:0] with a decimal value of 0, 2, or 5.

Recovery from Holdover

When in holdover mode, and an enabled translation profile

becomes available, the device exits holdover operation. The

loop controller restores the DPLL to closed-loop operation, which

begins to lock onto the selected reference, and sequences the

recovery of all loop parameters based on the profile settings for

the active reference.

If Bit 1 = 1 in Register 0x2105 (for DPLL0) or Register 0x2205

(for DPLL1), the device does not automatically exit holdover

when a valid translation profile is available. However,

automatic recovery of a valid translation profile can occur after

clearing Bit 1.

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