AD9546SLASHPCBZ datasheet(124/205 Pages) AD

124 / 205 page

AD9546

Data Sheet

Rev. 0 | Page 124 of 205

N Divider in External Zero Delay Mode

There is no internal feedback divider associated with the DPLL

in external zero delay operation because the feedback path is

external. Therefore, there is no requirement to program the

N hitless control element. However, the user must still program

N buildout to ensure proper operation of the DPLL loop filter.

Program N buildout as follows (refer to Figure 85):

N Buildout = round((2 × Q × Ry × fOUTx)/(M × fREFy)) + 1

where:

round() is a function to round the value contained within the ()

to the nearest integer.

Q is the divide ratio of the Q divider.

Ry is the divide ratio of the R divider associated with the REFy

input in Figure 85.

fOUTx is the output frequency at the OUTxyP and/or OUTxyN

output.

M is the divide ratio of the M divider.

fREFy is the frequency at the REFy input.

The calculated value of N buildout cannot be less than 1 or

greater than 1,073,741,824.

DPLL LOOP FILTER

The loop filter for DPLL0 and DPLL1 consists of a digital

infinite impulse response (IIR) filter architecture. The digital

filter is analogous to the third-order analog loop filter shown in

Figure 89, where input is on the left (from the phase detector)

and output is on the right (to the VCO).

Figure 89. Third-Order Analog Loop Filter

Whereas the response of an analog loop filter is a function of

physical components subject to thermal drift and aging, the

response of a digital loop filter is a function of numeric coefficients

and is not subject to thermal drift and aging. Figure 90 is a block

diagram showing the digital loop filters and their control

elements.

For completeness, Figure 90 shows the fast acquisition control

block of the AD9546 as part of the loop filter control because

the fast acquisition feature dynamically adjusts the loop

bandwidth as part of the fast acquisition process (see the DPLL

Fast Acquisition Options section).

Generally, the response characteristics of a digital filter depend

solely on the numeric coefficients. However, the DPLL loop

filters are special in that they require additional input

parameters: a bandwidth scale factor and the numeric value of

the DPLL feedback divider (see the DPLL Feedback Divider (N

Divider) section for details). The DPLL automatically resets the

internal state of the loop filter when the loop is not active (for

example, during entry into holdover or freerun mode).

DPLL Loop Filter Base Coefficients

The response characteristic of a digital loop filter is a function of

digital coefficients. In the case of the AD9546, there are base

coefficients that establish a normalized frequency response

characteristic. The user scales the normalized response to

achieve an absolute response (see the DPLL Loop Filter

Bandwidth section).

The AD9546 allows two independent sets of base coefficients,

Loop Filter 0 (LF0) and Loop Filter 1 (LF1). Each set consists of

four coefficients: alpha, beta, gamma, and delta, where Alpha 0

associates with LF0, Alpha 1 with LF1, and so on. Each of the

four coefficients has two components: a significand and an

exponent. The user has access to the coefficients via the

addresses and bit ranges shown in Table 79.

Each DPLL has access to the LF0 and LF1 base coefficient sets,

per Figure 90. Thus, DPLL0 and DPLL1 can use either of the

base coefficient sets. The translation profiles (see the

Translation Profiles section) establish which base coefficient set

a DPLL uses. To select LF0 or LF1, use Bit 7 of the appropriate

translation profile at the start addresses shown in Table 74 plus

an offset of 3 (decimal). Logic 0 (default) selects LF0, and

Logic 1 selects LF1.

Table 79. Loop Filter Base Coefficients

Coefficient

Address Range

Bit Range

Alpha 0 Significand

0x0C00 to 0x0C01

0 to 15

Alpha 0 Exponent

0x0C02

0 to 7

Beta 0 Significand

0x0C03 to 0x0C04

0 to 15

Beta 0 Exponent

0x0C05

0 to 7

Gamma 0 Significand

0x0C06 to 0x0C07

0 to 15

Gamma 0 Exponent

0x0C08

0 to 7

Delta 0 Significand

0x0C09 to 0x0C0A

0 to 15

Delta 0 Exponent

0x0C0B

0 to 7

Alpha 1 Significand

0x0C0C to 0x0C0D

0 to 15

Alpha 1 Exponent

0x0C0E

0 to 7

Beta 1 Significand

0x0C0F to 0x0C10

0 to 15

Beta 1 Exponent

0x0C11

0 to 7

Gamma 1 Significand

0x0C12 to 0x0C13

0 to 15

Gamma 1 Exponent

0x0C14

0 to 7

Delta 1 Significand

0x0C15 to 0x0C16

0 to 15

Delta 1 Exponent

0x0C17

0 to 7

The AD9546 default settings provide values for LF0 and LF1,

resulting in a default response characteristic. The LF0 default

values yield an open-loop response characteristic with 70°

phase margin (nominal). The LF1 default values yield an open-

loop response characteristic with an 88.5° phase margin

(nominal). Furthermore, the LF1 default coefficients yield a

nearly flat closed-loop response with <0.1 dB peaking.

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