AD9546SLASHPCBZ datasheet(129/205 Pages) AD

129 / 205 page

Data Sheet

AD9546

Rev. 0 | Page 129 of 205

Whenever the AD9546 enters freerun or holdover mode, the

DPLL phase lock detector indicates an unlocked state.

For more information on how to choose the appropriate phase

lock threshold, fill rate, and drain rate values for a given

application, refer to the AN-1061 Application Note, Behavior of

the AD9548 Phase and Frequency Lock Detectors in the Presence

of Random Jitter.

DPLL Frequency Lock Detector

The operation of the frequency lock detector is identical to that

of the phase lock detector, with the following two exceptions:

•

The fill or drain decision is based on the period deviation

between the reference of the DPLL and the feedback

signals instead of the phase error at the output of the PFD.

•

The frequency lock detector is unaffected by the state of

the phase slew limiter.

Like the phase lock detector, the user has access to the 12-bit

(signed) instantaneous water level value of the frequency lock

detector via Register 0x310B to Register 0x310C (DPLL0) and

Figure 93, the pertinent water level values appear along the left

side of the tub.

The frequency lock detector indicates frequency lock status via

Bit 2 of Register 0x3100 for DPLL0 and Register 0x3200 for

DPLL1 (Logic 0 is unlocked, and Logic 1 is locked). However,

because Bit 2 is dynamic in nature, the recommendation is to

use the IRQ mechanism for frequency lock indication instead.

The IRQ mechanism observes the state of Bit 2 and latches the

state transitions. Specifically, Bit 2 of Register 0x3010 for

DPLL0 and Register 0x3015 for DPLL1 latches a status change

from frequency unlocked to frequency locked as a Logic 1.

Likewise, Bit 3 of the same registers latches a status change

from frequency locked to frequency unlocked as a Logic 1.

Because Bit 2 and Bit 3 are latched bits, however, they may

represent a condition that is no longer true. Therefore, the user

must clear the frequency locked and frequency unlocked status

via Bit 2 and Bit 3, respectively, of Register 0x200B for DPLL0

and Register 0x2010 for DPLL1. Otherwise, the user may lose

indication of subsequent state transitions by the frequency lock

detector (see the Interrupt Request (IRQ) section).

The difference between the period of the signal arriving at the

reference input to the DPLL and the period of the signal

arriving at the feedback input to the DPLL constitutes the

period error between the two signals. The period error relates

to fREF and the feedback frequency (fFB) as

Period Error = 1/fFB − 1/fREF

For any given period error sample, the frequency lock detector

either adds water with the fill bucket or removes water with the

drain bucket (one or the other, but not both). The decision of

whether to add or remove water depends on the frequency lock

threshold specified by the user via Bits[23:0] (unsigned integer)

of the appropriate source profile at the start address shown in

Table 78 plus an offset of 5 to 7 (decimal). The value of

Bits[23:0] is the desired frequency lock threshold in ps. Thus,

the frequency lock threshold extends from 0 ps to 16.7 µs. The

frequency lock threshold represents the absolute value of the

period error between the reference and feedback signals at the

input to the DPLL as follows:

Frequency Lock Threshold = |Period Error|/10−12

For example, consider a nominal frequency at the reference

input to the DPLL of 80 kHz. Under a stable lock condition, the

frequency at the reference and feedback inputs to the DPLL are

equal. To configure the frequency lock detector to make fill or

drain decisions when the feedback and reference frequency at

the input to the DPLL differ by 100 Hz, establish the frequency

lock threshold for a 100 Hz deviation by choosing fREF = 80 kHz

and fFB = 80.1 kHz (or 79.9 kHz).

Frequency Lock Threshold = |Period Error|/10−12

= |1/fREF − 1/fFB|/10−12

= |1/80,000 − 1/80,100|/10−12

= 15,605 (nearest integer)

= 0x 00 3CF5 (hexadecimal)

For more information on how to choose the appropriate

frequency lock threshold, fill rate, and drain rate values for a

given application, refer to AN-1061 Application Note.

FREERUN TUNING WORD

The closed switch in Figure 91 indicates that the DPLL is

operating in closed-loop mode, where the loop filter delivers

FTWs in real time to the NCO. In open-loop operation, the

switch is in the open position and the FTW processor provides

a static FTW to the NCO. The loop controller opens or closes the

switch as needed. For example, when the DPLL is in freerun

mode (that is, Bit 0 = 1 of Register 0x2105 or Register 0x2205),

the loop controller opens the switch and the FTW processor

routes the freerun tuning word to the NCO.

In this case, the freerun tuning word establishes the NCO output

frequency, fNCO. The user sets the value of the freerun tuning

word via Bits[45:0] (unsigned integer) in Register 0x1000 to

fNCO ≈ fS × FTW0/248

where:

fNCO is the NCO output frequency.

fS is the system clock frequency.

FTW0 represents the value of the 46-bit freerun tuning word.

The preceding fNCO formula is an approximation (≈) because

the exact NCO output frequency differs slightly (see the DPLL

NCO section).

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