AD9546SLASHPCBZ datasheet(130/205 Pages) AD

130 / 205 page

AD9546

Data Sheet

Rev. 0 | Page 130 of 205

For example, given a system clock frequency of 2.3 GHz and a

desired NCO output frequency of 245.76 MHz, solve the fNCO

equation for FTW0 to yield the following value of the freerun

tuning word:

FTW0 = 248 × (fNCO/fS)

(21)

= 248 × (245.76 × 106/(2.3 × 109))

= 30,076,213,163,657 (nearest integer)

= 0x 1B5A AA00 7689 (hexadecimal)

Although the tuning resolution of the NCO is 48 bits, the

freerun tuning word is only 46 bits because, under all normal

operating conditions, the two most significant bits of the freerun

tuning word calculation (see Equation 21) are Logic 0. Therefore,

even though the NCO tuning word is 48 bits, the freerun

tuning word uses only the 46 LSBs of the NCO tuning word.

The value of freerun tuning word must satisfy the constraints

imposed by the NCO SDM (see the DPLL NCO section).

DPLL FAST ACQUISITION OPTIONS

Fast Acquisition Overview

Certain applications necessitate low loop bandwidths less than

1 Hz (for example, an application where the input reference to

the DPLL originates from a GPS/GNSS receiver with a 1 pulse

per second output). A 1 Hz reference requires a loop bandwidth

much less than 1 Hz, which can lead to frequency acquisition and

phase lock times in the range of minutes to hours.

To overcome the long acquisition time imposed by a sub 1 Hz

loop bandwidth, the AD9546 provides a built in fast acquisition

feature that greatly reduces the lock time of the DPLL. The fast

acquisition feature automatically changes the DPLL loop filter

bandwidth in a controlled manner. When the fast acquisition

feature is active (see the Fast Acquisition Bandwidth Control

section) the fast acquisition controller uses the following

features to control the fast acquisition process:

•

DPLL loop bandwidth

•

Fast acquisition excess bandwidth

•

Fast acquisition lock settle time

•

Fast acquisition timeout

The controller begins the fast acquisition process by applying a

user defined excess bandwidth factor to the specified DPLL loop

filter bandwidth (see the DPLL Loop Filter Bandwidth section in

the DPLL Loop Filter section). The controller then successively

reduces the excess bandwidth until it reaches the specified DPLL

loop filter bandwidth. At each step in the bandwidth reduction

process, however, the controller waits for the DPLL phase

detector to indicate lock status before moving on to the next

step (note the fast ACQ x functional blocks in Figure 90).

Fast Acquisition Status Indicators

While the fast acquisition controller is in the process of

performing a fast acquisition, status Bit 4 is Logic 1 in

Bit 4 relates to the IRQ function (see the Interrupt Request

(IRQ) section) through Bit 2 (fast acquisition started) and Bit 3

(fast acquisition completed) in Register 0x3012 (for DPLL0)

and Register 0x3017 (for DPLL1). Because Bit 2 and Bit 3 are

latched, the user must use Bit 2 and Bit 3, respectively, of

clear the latched state. Otherwise, the user cannot observe

subsequent state transitions of Bit 4.

Fast Acquisition Bandwidth Control

The fast acquisition feature is active when the user sets the fast

acquisition excess bandwidth parameter to a nonzero value.

The fast acquisition excess bandwidth parameter is Bits[3:0]

(unsigned integer) in the appropriate translation profile at the

start address shown in Table 74 plus an offset of 22 (decimal).

When the fast acquisition excess bandwidth parameter is

nonzero, the fast acquisition controller uses the fast acquisition

excess bandwidth parameter value to define the maximum

starting loop bandwidth (BW0) as follows:

BW0 = DPLL Loop Bandwidth × 2 fastacquisitionexcessbandwidthparameter

For example, given a DPLL loop bandwidth of 0.0001 Hz

(100 µHz) and a fast acquisition excess bandwidth parameter

value of 9, find the value of BW0 as follows:

BW0 = DPLL Loop Bandwidth × 2 fastacquisitionexcessbandwidthparameter

= 0.0001 Hz × 29

= 0.0512 Hz

In the preceding example, when the DPLL begins the signal

acquisition process, the starting loop bandwidth for the fast

acquisition sequence is 512 times wider than the final value.

After the DPLL acquires phase lock, the fast acquisition

controller tightens the loop bandwidth by a factor of two and

waits for phase lock. This bandwidth tightening process repeats

until the loop bandwidth reaches the specified DPLL loop

bandwidth. By using wider loop bandwidths during the signal

acquisition process, the fast acquisition feature achieves frequency

and phase lock much quicker than normal DPLL operation

without the fast acquisition feature.

The phase lock characteristic of the loop is subject to the DPLL

lock detector settings (see the DPLL Lock Detectors section).

Fast Acquisition Settling Time Control

Because each step in the fast acquisition process relies on phase

lock indication to proceed to the next step, the phase lock

indication must not chatter. That is, a noisy reference can cause

the phase lock indicator to switch intermittently between lock

and unlock until the loop settles to a stable lock condition. If

the lock indicator chatters, the chatter can cause the fast

acquisition controller to advance prematurely.

To help minimize the effect of a chattering phase lock indication,

the fast acquisition controller allows the user to specify a lock

indication settling time via Bits[2:0] (unsigned integer) in the

appropriate translation profile at the start address shown in

Table 74 plus an offset of 23 (decimal).

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