AD9546SLASHPCBZ datasheet(132/205 Pages) AD

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AD9546

Data Sheet

Rev. 0 | Page 132 of 205

DPLL PHASE OFFSET CONTROL

In general, the feedback loop of the DPLL (like the APLL) tends

to force the average phase offset between the two inputs of the

digital phase detector to zero (see Figure 94). As a result, assuming

Integer N operation (that is, the N divider is not fractional), the

DPLL input and output signals are edge aligned (or exhibit a

constant time offset due to path latency).

The AD9546 DPLLs provide the ability to impose a programma-

ble time offset (tOFST) between the input and feedback signals by

means of a summing node at the feedback input of the digital

phase detector. To insert a time offset, use Bits[39:0] (signed) of

0x1415 to Register 0x1419 (for DPLL1). The value of Bits[39:0]

has units of ps.

Two other sources for applying a phase offset also feed the

summing node (not explicitly shown in Figure 94). One is via

the source profiles (see the Skew Adjustment section of the

Source Profiles section), and the other is via the delay compens-

ation feature (see the Delay Compensation section).

Because the DPLL feedback loop results in an average offset of

zero between the two inputs of the digital phase detector, tOFST

translates to the DPLL output with the polarity shown in Figure 94.

The signed nature of Bits[39:0] allows the user to advance or

delay the DPLL output signal relative to its input. A positive

value for tOFST delays the output signal relative to the input signal.

That is, the output edge occurs later. Conversely, a negative value

advances the output signal relative to the input signal. Therefore,

the output edge occurs earlier.

The relationship between tOFST (sec) and the programmed value

for the DPLL phase offset (Bits[39:0]) is

DPLL Phase Offset = tOFST/10−12

For example, find the value of the DPLL phase offset necessary

to advance the output signal by 75 ns (that is, tOFST = −75 ns).

DPLL Phase Offset = (−75 × 10−9)/10−12

= −75,000

= 0x FF FFFE DB08 (hexadecimal)

DIGITAL

PHASE

DETECTOR

DIGITAL

LOOP

FILTER

SYSTEM

CLOCK

NUMERIC

COEFFICIENTS

NCO

LOCK

DETECTORS

FTW

PROCESSOR

LOOP

CONTROLLER

XOA XOB

AD9546

TDC

48-BIT

FTW

FREERUN TUNING WORD

DIGITAL CROSS

POINT MUX

NOTES

1. A RANGE OF BITS USES A COLON SEPARATOR

2. REGISTER ADDRESSES ARE SPECIFIC TO DPLL0

PHASE OFFSET

N DIVIDER

tOFST

REG 0x1019 TO 0x1015, BITS[39:0]

REG 0x1005 TO 0x1000, BITS[45:0]

Figure 94. DPLL Phase Offset Feature

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