AD9546SLASHPCBZ datasheet(131/205 Pages) AD

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Data Sheet

AD9546

Rev. 0 | Page 131 of 205

The value of Bits[2:0] tells the fast acquisition controller how

long to observe a nonchanging phase lock indication before

moving on to the next step. Table 82 show the available settling

time durations.

Table 82. Fast Acquisition Lock Detect Settling Time

Bits[2:0]

Settle Time

1 ms

10 ms

50 ms

100 ms

500 ms

1 sec

10 sec

50 sec

During operation, if the DPLL indicates a phase unlock within

the settling period, the fast acquisition controller does not

advance to the next step. Instead, the controller resets the

settling timer, waits for the next indication of phase lock, and

invokes the settling period again. This process continues until

the phase lock remains for the full duration of the prescribed

settling time.

Fast Acquisition Timeout Control

To prevent the fast acquisition controller from stalling because

the DPLL fails to reach a phase locked condition, the controller

has a timeout mechanism. That is, at each step in the fast

acquisition process, the fast acquisition controller waits for the

DPLL to phase lock (and settle), but only up to a user defined

maximum amount of time.

The user specifies the maximum time for the fast acquisition

controller to wait for phase lock via Bits[6:4] (unsigned integer)

in the appropriate translation profile at the start address shown

in Table 74 plus an offset of 23 (decimal).

The available timeout values appear in Table 83. If the fast

acquisition controller does not observe phase lock and settling

within the prescribed timeout interval, the fast acquisition

controller automatically advances to the next step in the fast

acquisition process. When the fast acquisition controller

reaches the final bandwidth step and the DPLL indicates phase

lock within the specified settle time, the fast acquisition

controller sets status Bit 5 (fast acquisition complete) of

Table 83. Fast Acquisition Timeout

Bits[6:4]

Settle Time

10 ms

50 ms

100 ms

500 ms

1 sec

10 sec

50 sec

100 sec

Fast Acquisition Trigger

The Fast Acquisition Timeout Control section describes the

timing of the fast acquisition process but not what triggers the

process. The user controls what triggers the fast acquisition

process via Bits[3:0] of Register 0x2106 (for DPLL0) and

•

Bit 0: fast acquisition from freerun

•

Bit 1: fast acquisition from holdover

•

Bit 2: fast acquisition during first acquisition

•

Bit 3: fast acquisition when no distribution outputs are

toggling

The fast acquisition controller treats the specific restrictions

implied by Bits[3:0] in logical OR fashion. That is, the

controller obeys all restrictions that apply per the set bits. Note

that when all four of these bits are Logic 0, no restrictions

apply. That is, the fast acquisition controller is completely

unrestricted, and the DPLL always uses fast acquisition (if

enabled). However, making any one of these bits Logic 1 puts

the fast acquisition controller into a restricted operating mode

where it must obey the restrictions explicitly as follows.

Fast acquisition triggers under the following four sets of

conditions:

•

When Bit 0 = 1 and the DPLL enters closed-loop operation

from freerun mode, fast acquisition triggers.

•

When Bit 1 = 1 and the DPLL enters closed-loop operation

from holdover mode, fast acquisition triggers.

•

When Bit 2 = 1 and this is the first execution of the fast

acquisition process, fast acquisition triggers. That is, the

fast acquisition controller has not completed a fast

acquisition sequence previously (more specifically, when

the fast acquisition complete status bit is Logic 0). When

the fast acquisition complete status bit is Logic 1, the user

can clear it by writing Logic 1 to Bit 3 (autoclearing) of

DPLL1). Setting Bit 3 = 1 provides a mechanism to have

subsequent first acquisition events.

•

When Bit 3 = 1 and all clock distribution outputs of the

corresponding PLL channel are not toggling, fast

acquisition triggers.

As an example of fast acquisition trigger control, assume Bit 1

and Bit 2 are both Logic 1 and that DPLL enters closed-loop

operation from freerun mode, which does not satisfy the first

condition. However, because there is a second restriction, and

the device treats the restrictions in logical OR fashion, the

status of the second constraint applies. As such, if the entry of

the DPLL into closed-loop operation from freerun mode

happens to be the first acquisition of the DPLL, a fast

acquisition is in effect (otherwise, a normal acquisition results).

Next, assume the DPLL enters closed-loop operation from

holdover, which satisfies the first condition. As such, the DPLL

employs fast acquisition (the first acquisition restriction is

immaterial in this case).

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