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SH7041A データシート(PDF) 424 Page - Renesas Technology Corp |
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SH7041A データシート(HTML) 424 Page - Renesas Technology Corp |
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424 / 923 page  386 Input capture signal TCNT φ TGR TGF flag TGI interrupt N N Figure 12.70 TGI Interrupt Timing (Input Capture) Setting Timing for Overflow Flag (TCFV)/Underflow Flag (TCFU): Figure 12.71 shows timing for the TCFV flag of the timer status register (TSR) due to overflow, as well as TCIV interrupt request signal timing. Figure 12.72 shows timing for the TCFU flag of the timer status register (TSR) due to underflow, as well as TCIU interrupt request signal timing. Figure 12.73 shows timing for the TCFV flag of TSR4 due to underflow in complementary PWM mode, as well as TCIV interrupt request signal timing. Overflow signal TCNT (underflow) TCNT input clock φ TCFV flag TCIV interrupt H'FFFF H'0000 Figure 12.71 TCIV Interrupt Setting Timing |
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