SH7041A datasheet(729/923 Pages) RENESAS

部品番号	SH7041A

部品情報	Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

PDF	923 Pages

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メーカー	RENESAS [Renesas Technology Corp]

ホームページ	http://www.renesas.com

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Bit 5: ESU1

Description

Erase setup release (Initial value)

Erase setup

[Setting condition] When FWE=1 and SWE=1

• Bit 4—Program Setup Bit 1 (PSU1): Prepares for a transition to program mode (applicable

addresses: H'00000–H'1FFFFF). Do not set the SWE, ESU1, EV1, PV1, E1, or P1 bit at the

same time.

Bit 4: PSU1

Description

Program setup release (Initial value)

Program setup

[Setting condition] When FWE=1 and SWE=1

• Bit 3—Erase-Verify 1 (EV1): Selects erase-verify mode transition or release (applicable

addresses: H'00000–H'1FFFF). Do not set the SWE, ESU1, PSU1, PV1, E1, or P1 bit at the

same time.

Bit 3: EV1

Description

Erase verify mode release (Initial value)

Transition to erase verify mode

[Setting condition] When FWE=1 and SWE=1

• Bit 2—Program-Verify 1 (PV1): Selects program-verify mode transition or release (applicable

addresses: H'00000–H'1FFFF). Do not set the SWE, ESU1, PSU1, EV1, E1, or P1 bit at the

same time.

Bit 2: PV1

Description

Program verify mode release (Initial value)

Transition to program verify mode

[Setting condition] When FWE=1 and SWE=1

SH7041A データシート(PDF) 729 Page - Renesas Technology Corp