L6364 datasheet(12/60 Pages) STMICROELECTRONICS

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SPI Communication

Internal registers (see Table 32. Register map) are provided to observe and control the L6364 state.

These register settings are read and written via the SPI interface, where the L6364 is the SPI slave. The

operating voltage level for inputs and outputs on the SPI interface is set by the VDIG pin. Usually, this pin is

directly connected either to the V5V or V3V3 pins (Section 23 Typical Applications). However, full functionality

of the IC is guaranteed even when VDIG pin is connected to 2.5 V, or 3.3 V, or 5.0 V or 5.5 V rail, although the

internal core works at the V3V3 rail.

The detailed timing diagram is shown in Figure 5 Data is shifted into an internal shift register from input MOSI on

each rising SCK edge. Data is made available on pin MISO at each falling SCK edge. Note that the MISO line is

only driven when the slave specific select line is SS='0', which allows other SPI slaves to share the same SPI bus.

The MSB of the address byte is a WR/RDn bit, where a '1' indicates that each byte is written to the registers.

Valid data is always made available on the MISO line independent of the WR/RDn bit.

Where a register is written and read in the same operation, then the read value is the old register value. During

read operations, the level of the MOSI line is ignored for the data bytes.

The byte sequence for data transmission is shown in Figure 6. Each transmission sequence consists of a falling

SS edge which synchronizes transmission, followed by a target register address byte.

During the transmission of the address byte from the microcontroller to the L6364, the status register contents are

sent from the L6364 to the microcontroller.

Figure 5. Register programming.

tSS

tms tmh

tsh

SCK

(microcontroller)

MOSI

(microcontroller)

tcl

tch

MSB

LSB

HiZ

don’t care

MSB

LSB

HiZ

tmd

MISO

(L6364)

don’t care

6.1

Multiple byte exchange

Multiple registers at consecutive addresses can be read or written by extending the access as shown in Figure 6;

bytes are written on the rising SCK clock edge of the eighth bit of each byte.

With the WR/RDn bit set, a simultaneous read/write operation is started. Now, with a multiple byte exchange, it is

possible to both read and write the values of multiple register bytes in one operation.

This is particularly useful with larger M-sequence types where there is limited time available for the SPI exchange.

L6364

SPI Communication

DS13363 - Rev 4

page 12/60

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