L6364 datasheet(21/60 Pages) STMICROELECTRONICS

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8.2.6

Single octet UART mode state machine

Figure 8. Single octet UART mode state diagram

Receive mode

Receive interim

Receive wait

IO-Link mode

IOListen

+do : UART in reads data on CQ

line, copies result to FR0

Notes :

Initialization

CCTL:SGL=‘1’

+do : UART reads data in

on CQ line and copies result

to FR0

Notes :

Notes : waiting for response from microcontroller,

either read from or write to FR0.

Master

octet rcvd

FR0 read

SIO mode

SIOActive

SIOListen

Short circuit/

Wake-up

trestart

elapsed

+entry : start restart timer (trestart)

+entry : HS,LS switches are off

+do

: UART reads data on CQ line,

copies to FR0

+entry : set data interrupt (STATUS:DAT=‘1’)

+do

: UART reads data in on CQ line

SIO mode set by the

microcontroller

Transmit mode

Transmitting

(buffer full)

Transmitting

(terminating)

Transmitting

(buffer empty)

Transmitting wait

Notes : the CQ line is driven according

to the setting of the CCTL:HS and

CCTL:LS bits

Notes : the L6364 has received a short-circuit via a

wake-up request from the master

+do : UART sends

+do : UART sends data out on CQ line

Notes : waiting for response from

microcontroller, either write to FR0 or

LINK:END

+entry : set data interrupt (STATUS:DAT=‘1’)

+do

: UART waits

Notes : waiting for response from

microcontroller, either write to FR0 or

LINK:END

Write FR0

UART done

UART

done

END

written

FR0

written

IO-Link mode set by

the microcontroller

Complete master

octet received

Complete valid master

octet received

UART done

END written

FR0 written

CCTL:SIO='0'

CCTL:SIO=‘1'

Parity error, stop error, timeout or buffer over-run

signaled with CHK='1'. Microcontroller responds with

LINK:END and discards received octets

Short-circuit signaled with SSC, overtemperature with

SOT. Microcontroller typically ignores

8.2.7

Synchronization in single octet UART mode

The L6364 uses a PLL (phase-locked loop) to continuously lock the UART receive and transmit frequency to the

master frequency.

A few octet values (00h, 80h, e0h, f8h and feh) do not provide information which can be used to correct the PLL

frequency, and a continuous sequence of these values could prevent the PLL performing frequency tracking for

some time.

In IO-Link operation, however, it is not possible to create such M-sequences as the defined format of the

M-sequence, and in particular the checksum, guards against this.

A continuous sequence of these octets is possible when the single octet UART mode is used in a proprietary

mode, eg. for code download.

In this case, the insertion of a synchronization octet (aah) at least every 75 ms is required, taking into account

a worst case dissipation change (1W) in combination with a worst case oscillator temperature drift. The interval

of 75 ms is equivalent to 240 octets at 38.4kBaud assuming an inter-frame delay of 1 bit. We recommend the

insertion of a synchronization octet every 32 octets.

8.3

Transparent UART mode

The L6364 supports an operating mode for transparent communication of UART frames.

In this mode, the frames are received and transmitted from a UART peripheral in the microcontroller, and the

function of the DUAL PHY device is reduced to that of a physical level converter.

This mode is supported by dual use of the MOSI and MISO pins, maintaining the low overall pin-count and a

restricted use of microcontroller resources.

Transparent mode is entered by setting the CCTL:TRNS register bit to '1' via the SPI. In this mode the IO-Link

state machine in the L6364 and the PLL are placed in reset.

The interrupt line and status monitoring for reset, short-circuit, overtemperature and undervoltage events continue

to function.

L6364

Transparent UART mode

DS13363 - Rev 4

page 21/60

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