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ST25R3916B-AQWT データシート(PDF) 52 Page - STMicroelectronics |
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ST25R3916B-AQWT データシート(HTML) 52 Page - STMicroelectronics |
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52 / 165 page  Application information ST25R3916B ST25R3917B 52/165 DS13541 Rev 7 Figure 14. Exchange of signals with a microcontroller The first two bits of the first byte transmitted after the BSS high to low transition define the SPI operation mode. All Read and Write modes support address auto incrementing, which means that if, after the address and first data byte some additional data bytes are sent (or read), they are written to (or read from) addresses incremented by 1. Table 12 shows available SPI operation modes. Register read and write operations are possible in all ST25R3916B and ST25R3917B operation modes. FIFO and PT_memory operations are possible in case en (bit 7 of the Operation control register) is set and the crystal oscillator is stable. Some direct commands are accepted in all operation modes, others require en (bit 7 of the Operation control register) to be set and the crystal oscillator to be stable (see Table 14). MS51643V2 MOSI MISO I/O MOSI MISO MISO MOSI Separate SPI input and output signals to MCU Bidirectional data IO signal to MCU Table 12. SPI operation modes Mode Pattern (communication bits) Related data Mode Trailer M1 M0 C5 C4 C3 C2 C1 C0 Register write 0 0 A5 A4 A3 A2 A1 A0 Data byte (or more bytes in case of auto-incrementing). Register read 0 1 A5 A4 A3 A2 A1 A0 FIFO load 10000 000 One or more bytes of FIFO data. PT_memory load A-config 10100 000 Passive target memory, locations from 0 on. PT_memory load F-config 10101 000 Passive target memory, locations from 15 on. PT_memory load TSN data 10101 100 Passive target memory, locations from 36 on. The additional address allows reload of the TSN random numbers without rewriting the whole PT_memory. |
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