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ST25R3916B-AQWT データシート(PDF) 28 Page - STMicroelectronics |
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ST25R3916B-AQWT データシート(HTML) 28 Page - STMicroelectronics |
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28 / 165 page ![]() Application information ST25R3916B ST25R3917B 28/165 DS13541 Rev 7 The gain in the second and third stage is 23 dB and can be reduced in six 3 dB steps. Gain of these two stages is included in AGC and Squelch loops or can be manually set in Receiver configuration register 4. Sending of direct command Reset RX Gain is necessary to initialize the AGC, Squelch and RSSI block. Sending this command clears the current Squelch setting and loads the manual gain reduction from Receiver configuration register 4. Second stage has a second order low-pass filtering characteristic, the pass band is adjusted according to subcarrier frequency using the bits lp2 to lp0 of the Receiver configuration register 1. See Table 5 for -1 dB cut-off frequency for different settings. Digitizing stage The digitizing stage produces a digital representation of the sub-carrier signal coming from the receiver. This digital signal is then processed by the receiver framing logic. The digitizing stage consists of a window comparator with adjustable digitizing window (five possible settings, 3 dB steps, adjustment range from ±33 to ±120 mV). The adjustment of the digitizing window is included in the AGC and Squelch loops. The digitizing window can also be set manually in the Receiver configuration register 4. AGC, Squelch and RSSI As mentioned above, the second and third gain stage gain and the digitizing stage window are included in the AGC and Squelch loops. Eleven settings are available. The default state features minimum digitizer window and maximum gain. The first four steps increase the digitizer window in 3 dB steps, the next six steps reduce the gain in the second and third gain stage, again in 3 dB steps. The initial start setting for Squelch and AGC is defined in Receiver configuration register 4. The Gain reduction state register displays the actual state of gain resulting from Squelch, AGC and initial settings in Receiver configuration register 4. 10 1 7 MHz Others Not used Table 6. First and third zero setting rec1<3>z600k rec1<2>h200 rec1<1>h80 rec1<0>z12k First stage zero Third stage zero 00 0 0 60 kHz 400 kHz 0 1 0 0 200 kHz 0 0 1 0 40 kHz 80 kHz 00 0 1 12 kHz 200 kHz 0 0 1 1 80 kHz 0 1 0 1 200 kHz 10 0 0 600 kHz 400 kHz 1 1 0 0 200 kHz Others Not used Table 5. Low-pass control (continued) rec1<5>lp2 rec1<4>lp1 rec1<3>lp0 -1 dB point |
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