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ST25R3916B-AQWT データシート(PDF) 85 Page - STMicroelectronics |
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ST25R3916B-AQWT データシート(HTML) 85 Page - STMicroelectronics |
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85 / 165 page  DS13541 Rev 7 85/165 ST25R3916B ST25R3917B Application information 164 4.5.12 EMD suppression configuration register Register space: B Address: 05h Type: RW Table 38. EMD suppression configuration register Bit Name Default Function Comments 7 emd_emv 0 0: Disable EMD suppression 1: Enable EMD suppression according to EMVCo Bits no_rx_par and no_crc_rx must be set to 0, and bit nrt_emv must be set to 1 when emd_emv is enabled 6 rx_start_emv 0 0: Reception is enabled (I_rxs) only if the first 4 bits of the frame are error free 1: Reception is enabled (I_rxs) also if there is an error in the first four bits of the frame Applies to ISO-A 106k only. Must be set to 1 for EMVCo compliance. 5RFU 0 - - 4RFU 0 - - 3 emd_thld3 0 If the received frame is less than emd_thld<3:0> bytes long then EMD suppression will trigger on reception errors Must be set to 4 for EMVCo compliance. 2 emd_thld2 0 1 emd_thld1 0 0 emd_thld0 0 |
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