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ST25R3916B-AQWT データシート(PDF) 27 Page - STMicroelectronics

部品番号 ST25R3916B-AQWT
部品情報  NFC reader for payment, consumer and industrial applications
PDF  165 Pages
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メーカー  STMICROELECTRONICS [STMicroelectronics]
ホームページ  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

ST25R3916B-AQWT データシート(HTML) 27 Page - STMicroelectronics

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DS13541 Rev 7
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ST25R3916B ST25R3917B
Application information
164
Demodulation stage
The first stage performs demodulation of the tag subcarrier response signal, superimposed
on the HF field carrier. Two different blocks are implemented for the AM demodulation:
peak detector
AM/I or PM/Q demodulator mixer.
The choice of the used demodulator is made by the Receiver configuration register 2 bit
amd_sel.
The peak detector performs AM demodulation using a peak follower. Both the positive and
negative peaks are tracked to suppress any common mode signals. Its demodulation gain is
G = 0.7 and the input is taken from RFI1 demodulator input only.
The AM demodulator mixer uses synchronous rectification of both receiver inputs (RFI1 and
RFI2). Its gain is G = 0.55. The PM demodulation is also done by a mixer. The PM
demodulator mixer has differential outputs with 60 mV differential signal for 1% phase
change (16.67 mV / °).
The I/Q demodulation is composed of two mixer circuits, driven with a 90° shifted local
oscillator (LO) signals derived from the crystal oscillator. The outputs of the two mixers are
connected to two equal base band reception chains and to the decoding logic.
Filtering and gain stages
The receiver chain has band pass filtering characteristics. The filtering is optimized to pass
subcarrier frequencies while rejecting carrier frequency, low frequency noise and DC
component. Filtering and gain is implemented in three stages, the first and the last stage
have first order high pass characteristics while the mid stage has second order low-pass
characteristic.
The gain and filtering characteristics can be optimized depending on the application by
writing the Receiver configuration register 1 (filtering), Receiver configuration register 3
(primarily gain in first stage) and Receiver configuration register 4 (gain in second and third
stage).
The gain of first stage is around 20 dB and can be reduced in six 2.5 dB steps. There is also
a special boost mode available, which increases the max gain by additional 5.5 dB. The first
stage gain can only be modified by writing Receiver configuration register 3. The default
setting of this register is the minimum gain. Default first stage zero is located at 60 kHz, it
can also be lowered to 40 or 12 kHz by writing option bits in the Receiver configuration
register 1. The first stage can be reconfigured to second order high-pass at 600 kHz by
option bit z600k. The control of the first and third stage zeros is done with common control
bits (see Table 6).
Table 5. Low-pass control
rec1<5>lp2
rec1<4>lp1
rec1<3>lp0
-1 dB point
0
0
0
1200 kHz
0
0
1
600 kHz
0
1
0
300 kHz
10
0
2 MHz



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