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データシートサーチシステム |
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RA4E2 データシート(PDF) 53 Page - Renesas Technology Corp |
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RA4E2 データシート(HTML) 53 Page - Renesas Technology Corp |
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53 / 90 page  Table 2.31 IIC timing(2) Conditions: VCC = 3.00 to 3.60 V Setting of the SDA0_D, SCL0_D pins is not required with the Port Drive Capability bit in the PmnPFS register. Parameter Symbol Min Max Unit IIC (Hs-mode) BFCTL.HSME = 1 SCL input cycle time tSCL 55(57) × tI3Ccyc — ns SCL input high pulse width Cb = 400 pF tSCLH 43(44) × tI3Ccyc — ns Cb = 100 pF 23(24) × tI3Ccyc — SCL input low pulse width Cb = 400 pF tSCLL 64(65) × tI3Ccyc — ns Cb = 100 pF 32(33) × tI3Ccyc — SCL rise time Cb = 400 pF tSrCL — 80 ns Cb = 100 pF — 40 SDA rise time Cb = 400 pF tSrDA — 160 ns Cb = 100 pF — 80 SCL fall time Cb = 400 pF tSfCL — 80 ns Cb = 100 pF — 40 SDA fall time Cb = 400 pF tSfDA — 160 ns Cb = 100 pF — 80 SCL, SDA input spike pulse removal time tSP 0 1(1) × tI3Ccyc ns Repeated START condition input setup time tSTAS 40 — ns STOP condition input setup time tSTOS 40 — ns Data input setup time tSDAS 10 — ns Data input hold time Cb = 400 pF tSDAH 0 150 ns Cb = 100 pF 0 70 SCL, SDA capacitive load Cb*1 — 400 pF Note: tI3Ccyc: I3C internal reference clock (I3Cφ) cycle. Note: Values in parentheses apply when INCTL.DNFS[3:0] is set to 0x3 while the digital filter is enabled with INCTL.DNFE set to 1. Note 1. Cb indicates the total capacity of the bus line. I3C_SDA0 I3C_SCL0 Sr tSfDA tSrDA tSTAS tSDAH tSDAS tSTOS tSfCL tSCLH tSCLH tSCLL tSCLL tSrCL 0.3 × VCC = MCS current source pull-up = Rp resistor pull-up Sr P 0.7 × VCC 0.3 × VCC 0.7 × VCC Figure 2.42 I2C bus interface input/output timing (Hs-mode) RA4E2 Datasheet 2. Electrical Characteristics R01DS0413EJ0110 Rev.1.10 Feb 28, 2023 Page 53 of 90 |
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