RA4E2 datasheet(87/90 Pages) RENESAS

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Table 3.2

Access cycles (2 of 3)

Peripherals

Address

Number of access cycles

ICLK = PCLK

ICLK > PCLK*1

Cycle

Unit

Related function

From

Read

Write

Read

Write

CANFD ECC

0x4012_F000

0x4012_FFFF

2 to 4

PCLKA

CANFD ECC Module

GPT16En,

GPT_OPS

0x4016_9000

0x4016_9FFF

4 to 7

2 to 4

PCLKA

General PWM 16-Bit

Timer n, Output Phase

Switching Controller

ADC12n, DAC12

0x4017_0000

0x4017_2FFF

2 to 5

2 to 4

PCLKA

12bit A/D Converter n,

12-bit D/A converter

Table 3.2

Access cycles (3 of 3)

Peripherals

Address

Number of access cycles

ICLK = FCLK

ICLK > FCLK*1

Cycle

Unit

Related function

From

Read

Write

Read

Write

FLAD, FACI

0x407F_C000

0x407F_EFFF

2 to 5

2 to 4

FCLK

Data Flash, Flash

Application Command

Interface

Note 1. If the number of PCLK or FCLK cycles is non-integer (for example 1.5), the minimum value is without the decimal point, and the

maximum value is rounded up to the decimal point. For example, 1.5 to 2. 5 is 1 to 3.

Note 2. When accessing a 16-bit register (FTDRHL, FRDRHL, FCR, FDR, LSR, and CDR), access is 2 cycles more than the value shown in

Table 3.2. When accessing an 8-bit register (including FTDRH, FTDRL, FRDRH, and FRDRL), the access cycles are as shown in

Table 3.2.

Note 3. When accessing the 32-bit register (SPDR), access is 2 cycles more than the value in Table 3.2. When accessing an 8-bit or 16-bit

RA4E2 Datasheet

Appendix 3. I/O Registers

R01DS0413EJ0110 Rev.1.10

Feb 28, 2023

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