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AM29PDL129H データシート(PDF) 34 Page - SPANSION |
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AM29PDL129H データシート(HTML) 34 Page - SPANSION |
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34 / 49 page ![]() 32 Am29PDL129H November 2, 2005 TEST CONDITIONS Table 16. Test Specifications Note: For 70 pF output load capacitance, 2 ns will be added to certain read-only operation parameters. KEY TO SWITCHING WAVEFORMS 2.7 k Ω CL 6.2 k Ω 3.6 V Device Under Test Note: Diodes are IN3064 or equivalent Figure 8. Test Setup, VIO = 2.7 – 3.6 V * For VIO = 1.65 – 1.95 Test Setup, the device is tested using CL only Test Condition All Speeds Unit Output Load 1 TTL gate Output Load Capacitance, CL (including jig capacitance) 30 pF Input Rise and Fall Times 5 ns Input Pulse Levels 0.0–3.0 V Input timing measurement reference levels 1.5 V Output timing measurement reference levels 1.5 V WAVEFORM INPUTS OUTPUTS Steady Changing from H to L Changing from L to H Don’t Care, Any Change Permitted Changing, State Unknown Does Not Apply Center Line is High Impedance State (High Z) VIO 0.0 V VIO/2 VIO/2 Output Measurement Level Input Figure 9. Input Waveforms and Measurement Levels |
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