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AM29PDL129H データシート(PDF) 35 Page - SPANSION

部品番号 AM29PDL129H
部品情報  128 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-only, Page Mode Simultaneous Read/Write Flash Memory with Enhanced VersatileIO Control and Dual chip Enable
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AM29PDL129H データシート(HTML) 35 Page - SPANSION

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November 2, 2005
Am29PDL129H
33
AC CHARACTERISTICS
CE1#/CE2# Timing
Read-Only Operations
Notes:
1.
Not 100% tested.
2.
See Figure 8 and Table 16 for test specifications
3.
Valid CE1#/CE2# conditions: (CE1#= VIL, CE2#= VIH) or (CE1#=
VIH, CE2#=VIL).
4.
Valid CE1#/CE2# transitions: (CE1#= CE2#= VIH) to (CE1#= VIL,
CE2#=VIH) or (CE1#= VIH, CE2#=VIL).
5.
Measurements performed by placing a 50 ohm termination on the
data pin with a bias of VCC/2. The time from OE# high to the data
bus driven to VCC/2 is taken as tDF.
6.
Valid CE1#/CE2# transitions: (CE1#= VIL, CE2#= VIH) or (CE1#=
VIH, CE2#=VIL) to (CE1#= CE2#= VIH).
7.
For 70 pF output load capacitance, 2 ns will be added to tACC, tCE,
tPACC, tOE values for all speed options.
Parameter
Description
All Speed Options
Unit
JEDEC
Std
tCCR
CE1#/CE2# Recover Time
Min
30
ns
CE1#
tCCR
tCCR
CE2#
Figure 10.
Timing Diagram for Alternating Between CE1# and CE2# Control
Parameter
Description
Test Setup
Speed Options
JEDEC
Std.
53
63
68
88
Unit
tAVAV
tRC
Read Cycle Time (Note 1)
Min
55
65
65
85
ns
tAVQV
tACC
Address to Output Delay (Note 3)
CE#, OE# = VIL
Max
55656585
ns
tELQV
tCE
Chip Enable to Output Delay (Note 4)
OE# = VIL
Max
60657085
ns
tPACC Page Access Time
Max
20
25
30
ns
tGLQV
tOE
Output Enable to Output Delay
Max
20
25
30
ns
tEHQZ
tDF
Chip Enable to Output High Z (Notes 1, 5, 6)
Max
16
ns
tGHQZ
tDF
Output Enable to Output High Z (Notes 1, 5)
Max
16
ns
tAXQX
tOH
Output Hold Time From Addresses, CE#/CE2#
or OE#, Whichever Occurs First (Notes 5, 6)
Min
5
ns
tOEH
Output Enable Hold Time
(Note 1)
Read
Min
0
ns
Toggle and
Data# Polling
Min
10
ns



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