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AM29PDL129H データシート(PDF) 38 Page - SPANSION

部品番号 AM29PDL129H
部品情報  128 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-only, Page Mode Simultaneous Read/Write Flash Memory with Enhanced VersatileIO Control and Dual chip Enable
PDF  49 Pages
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AM29PDL129H データシート(HTML) 38 Page - SPANSION

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Am29PDL129H
November 2, 2005
AC CHARACTERISTICS
Erase and Program Operations
Notes:
1. Not 100% tested.
2. See the “Erase And Programming Performance” section for more information.
Parameter
Speed Options
JEDEC
Std.
Description
53
63
68
88
Unit
tAVAV
tWC
Write Cycle Time (Note 1)
Min
55
65
65
85
ns
tAVWL
tAS
Address Setup Time
Min
0
ns
tASO
Address Setup Time to OE# low
during toggle bit polling
Min
15
ns
tWLAX
tAH
Address Hold Time
Min
30
35
ns
tAHT
Address Hold Time From CE1#, CE2#, or OE# high
during toggle bit polling
Min
0
ns
tDVWH
tDS
Data Setup Time
Min
25
30
ns
tWHDX
tDH
Data Hold Time
Min
0
ns
tOEPH
Output Enable High during toggle bit polling
Min
10
ns
tGHWL
tGHWL
Read Recovery Time Before Write
(OE# High to WE# Low)
Min
0
ns
tELWL
tCS
CE1# or CE2# Setup Time
Min
0
ns
tWHEH
tCH
CE1# or CE2# Hold Time
Min
0
ns
tWLWH
tWP
Write Pulse Width
Min
35
40
ns
tWHDL
tWPH
Write Pulse Width High
Min
20
25
ns
tSR/W
Latency Between Read and Write Operations
Min
0
ns
tWHWH1
tWHWH1 Programming Operation (Note 2)
Typ
6
µs
tWHWH1
tWHWH1 Accelerated Programming Operation (Note 2)
Typ
4
µs
tWHWH2
tWHWH2 Sector Erase Operation (Note 2)
Typ
0.5
sec
tVCS
VCC Setup Time (Note 1)
Min
50
µs
tRB
Write Recovery Time from RY/BY#
Min
0
ns
tBUSY
Program/Erase Valid to RY/BY# Delay
Max
90
ns



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