November 2, 2005

Am29PDL129H

39

AC CHARACTERISTICS

OE#

CE1# or CE2#

WE#

Addresses

Data

Valid

In

Valid

In

Valid PA

Valid RA

Valid

Out

Valid

In

CE# Controlled Write Cycles

WE# Controlled Write Cycle

Valid PA

Valid PA

Read Cycle

Note:

Figure 17.

Back-to-back Read/Write Cycle Timings

WE#

CE1# or CE2#

OE#

High Z

High Z

DQ7

DQ6–DQ0

RY/BY#

Complement

True

Addresses

VA

VA

VA

Status Data

Complement

Status Data

True

Valid Data

Valid Data

Note:

1. VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read

Figure 18.

Data# Polling Timings (During Embedded Algorithms)