CS5305GDWR28 datasheet(19/33 Pages) ONSEMI

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CS5305

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Table 1. Description of Fault Logic

Fault Modes

Stop

Switching

DRVON

Level

PWRGD

Level

Controller

Off

COMP Pin

Characteristics

Reset Method

Under Voltage Lockout

yes

low

low via Power Good

window comparator

n/a

−5.0 μA

Comp < 0.2 V

VID = 11111

yes

low

low via Power Good

window comparator

n/a

−5.0 μA

Comp < 0.2 V

Enable Low

yes

low

n/a

−5.0 μA

Comp < 0.2 V

Module Over Current

(set by OCSET)

yes

low

low via Power Good

window comparator

> 3.8 V

−5.0 μA

Comp < 0.2 V

Phase Over Current

(0.33 V limit)

terminate

pulse

high

n/a

not affected

External Share Fault

(SHARE > 3.8 V)

yes

low

low via Power Good

window comparator

n/a

−2.5 mA

remove external

3.8 V from SHARE

PWRGDS out of win-

dow range

high

low

n/a

not affected

Gate Outputs

The CS5305 is designed to operate with external gate

drivers. Accordingly, the gate outputs are capable of driving

a 100 pF load with typical rise and fall time of 15 ns.

DRVON

When the CS5305 is used with DRVON−compatible gate

drivers, the ability of the system to survive a fault in a

paralleled environment is greatly increased. The DRVON

signal tells the gate drivers to shut off both FETs while

entering a fault condition. This action takes the faulted VRM

“out of the picture,” allowing the system to operate until the

bad module can be replaced.

Digital to Analog Converter (DAC)

The output voltage of the CS5305 module is set by means

of a 5−bit, 1% DAC. The DAC pins are internally pulled up

to a 3.3 V rail through a blocking diode and a set of 50 kΩ

resistors. The blocking diode allows external pull up to a

bias voltage greater than 3.3 V and less than 13 V.

The output of the DAC is described in the Electrical

Characteristics section of the datasheet. These outputs are

consistent with the latest VRM specifications. The DAC

produces an output voltage 125 mV lower than the VID code

would indicate in order to produce an accurate PWRGD

output. The relationship between the VID code and the DAC

code is described by Figure 32 shown below. The shaded

area shows the acceptable range of output voltages.

In order to produce a workable VRM using the CS5305,

the designer is expected to use AVP as described earlier to

position the output voltage above the DAC output, resulting

in an output voltage somewhere in the middle of the

acceptable range.

125 mV

VID code

DAC output

MAX VOUT

MIN VOUT

VOUT

Figure 32. VRM 9.0 Output

Voltage Accuracy Requirements

The latest VRM specifications require a module to turn its

output off in the event of a 11111 VID code. When the DAC

sees such a code, the GATE pins stop switching and go low.

The DRVON signal also goes low, which turns off all FETs

on the module if the FET driver has an enable input. This

condition is described in Table 1.

PWRGD

According to the latest VRM specifications, the PWRGD

signal is to be asserted when the output voltage is within a

window defined by the VID code, as shown in Figure 33.

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