CS5305GDWR28 datasheet(31/33 Pages) ONSEMI

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CS5305

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Figure 49.

VOUT+ sense

VOUT− sense

VOUT+ sense

VOUT− sense

2.Differential noise across the PWM comparator can be

further reduced if the VOUT+ and VOUT− sense lines

going to CSREF and GND are paralleled to minimize

loop area. VOUT+ ripple information provided to the

PWM comparator via the CSREF pin needs to be

symmetric for all three phases or poor current sharing

between phases will occur. This can be accomplished

by placing the VOUT+ and VOUT− sense locations

symmetrically with respect to the three output

inductors. See Figure 49.

3.Frequency jitter could occur if the ROSC pin (2) and

OCSET pin (1) components are not properly located.

Most layouts will have two resistors in series from

ROSC to GND. Keep these two components as close

as possible to the IC and ensure a short ground

connection to the IC GND. Provision for a small cap

(1000 pF or less) from ROSC to GND can be placed

although this is rarely needed. If the ROSC capacitor

value is too large, the ROSC voltage reference will

oscillate.

4.The VCC (23) bypass capacitor (0.1 μF or greater)

should be located as close as possible to the IC. This

capacitor’s connection to GND must be as short as

possible. The most effective way to implement this

tight component placement is to via the GATE1, 2, 3

and DRVON runs to internal layers right at the IC

pins.

5.The switch nodes of all three phases must be sensed for

inductive current sensing. Care should be given to

how this information is brought to the CS5305.

Switch node voltages should not be routed

underneath or near the IC; however, the resistors in

the RC filter of CS1, 2, 3 must be reasonably close to

their associated capacitors so noise pick−up on the

CS1, 2, 3 pins is minimized. The best solution is to

locate the RC filter capacitors close to the CS1, 2, 3

pins and to place the respective resistors off to the side

of the IC.

6.A positive temperature coefficient thermistor can be

used for R11 (see Share Bus section) to compensate

for thermal variation in the inductor ESR. This

component should be placed near the one of the

inductors to achieve the best thermal coupling, and so

the best current sharing performance. Remote

placement with respect to the IC requires dedicated

parallel runs of GND and IFB to reduce share bus

noise sensitivity.

Thermal Considerations

Typically, the controller IC and the FET gate drivers do

not dissipate significant amounts of power, and do not

contribute greatly to module power dissipation. The main

components of concern are the switch FETs and the

inductors.

We have already reviewed the power calculations for

these components, but we haven’t related them to a thermal

solution. Standards exist limiting the maximum VRM

printed circuit board temperature (105°C is common), and

thus power dissipation becomes a thermal consideration in

addition to playing a part in overall module efficiency.

Power dissipation on the VRM results in heat radiation

to the surrounding air. Power dissipated by the components

is conducted to the PCB. The PCB acts as a heat sink and

provides a larger surface area for heat exchange to the

surrounding air. The PCB temperature is dependent on total

PCB power dissipation, the surface area of the PCB

available to act as a heat sink, the ambient temperature of

the surrounding air and the thermal resistance to ambient of

the PCB.

While it is possible to model power dissipation on the PCB

for efficiency purposes, it is very difficult to accurately

model thermal performance. In particular, thermal

resistance to ambient of the PCB varies widely. This

parameter depends on many factors: board shape, size and

material; copper weight; amount of exposed copper;

insulating characteristics of the solder mask layers; air flow

properties (amount, direction, PCB orientation to the

airflow); and even whether a particular component is

“hidden” behind others. In reality, modeling PCB resistance

to ambient is highly complex and the best way to guarantee

thermal performance is to actually build prototypes and

measure it directly.

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