CS5305GDWR28 datasheet(25/33 Pages) ONSEMI

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CS5305

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Figure 42.

No Load Cursor Marker

Full Load Cursor Marker

Trace 1: Optimal

Trace 2: CFB too large

Trace 3: CFB too small

Trace 4: CDRCMP too large, CCOMP too small

Trace 5: CDRCMP too small, CCOMP too large

Using the transient test tool, set up a current load step from

low current (1 A) to maximum load at the slew rate being

designed for. Set the current step at about 100 Hz with a duty

cycle of 10%. Converter response should be similar to that

shown in Figure 42.

Next, determine if there is a “bump” (trace 4 or trace 5) in

the output. Adjust CCOMP and CDRCMP to flatten out this

bump. If the “bump” is negative (trace 5), make CDRCMP

slightly larger and CCOMP slightly smaller. If you see a

positive “bump” (trace 4), make CDRCMP slightly smaller

and CCOMP slightly larger. If performance is better without

CDRCMP, just make C1 larger.

Once the bump is removed, look to see if the “pulse step”

magnitude is larger or smaller than the DC level (trace 2 or

trace 3). Make CFB slightly larger if the AC gain (trace 3) is

too large or slightly smaller if the AC gain (trace 2) is too

small. Once the output response resembles the “optimal”

trace (trace 1), the controller has been optimized for the

design from a static and dynamic response.

If the output appears to be jittering slightly prior to

optimizing transient response, make the previous

adjustments first, since they may solve the problem. If the

problem persists, decreasing the value of Rcsx across the

inductor will increase ramp amplitude, and jitter

performance should improve with increased ramp.

The second method uses a capacitor to “square up” the

COMP waveform and a series resistor and capacitor to tune

the VDRP waveform. These components are chosen

empirically based on observations of COMP and VDRP

performance.

First, set the test tool for a load current transient from no

load (1 A) to full load and observe the COMP waveform.

The COMP waveform should ideally be flat, or at worst

decrease slightly during a current increase transient. The

principle at work here is that the increase in current sense

information will generate a voltage that should exactly

cancel the droop voltage, and thus the COMP capacitor

voltage should not change. In reality, it is unlikely that every

manufactured module can be built to perfectly compensate

the droop voltage, and so the COMP voltage should exhibit

a small amplitude square wave during transient conditions.

If the COMP voltage is decreasing gradually, the current

sense information is too small to fully compensate for the

droop voltage, and the designer should add a capacitor

between VOUT and COMP. This capacitor is chosen

empirically, with 1 nF a good starting point. This capacitor

will pull the COMP pin down initially and “square up” the

COMP waveform as shown in Figure 43.

Figure 43.

Current Transient

COMP Ideal Waveform

COMP Uncorrected

Waveform

VOUT Uncorrected

Waveform

COMP Corrected

Waveform

VOUT Corrected

Waveform

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