CS5305GDWR28 datasheet(29/33 Pages) ONSEMI

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CS5305

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The input capacitance must be designed to conduct the

worst case input ripple current. This will require several

capacitors in parallel. In addition to the worst case current,

attention must be paid to the capacitor manufacturer’s

derating for operation over temperature.

As an example, let us define the input capacitance for a

12 V to 1.7V conversion at 81 A, or 27 A per phase at an

ambient temperature of 60°C. A droop voltage of 90 mV to

1.61 V and efficiency of 80% is assumed. Average input

current in the input filter inductor is:

IIN(AVE) +

(27 A)(3 phases)(1.61 V 12 V)

80%

+ 10.868 A

Input capacitor RMS ripple current is then

IIN(RMS) +

10.8682 ) 1.61 V

12 V

27 A * 10.868 A 2 * 10.868 A2

+ 13.347 A

If we consider a Sanyo SP series capacitor, the ripple

current rating for a 16SPS100M capacitor is 2820 mA at

100 kHz and 45°C. The derating factor is 0.85 for operation

up to 65°C, resulting in an effective ripple current rating of

2397 mA. We determine the number of input capacitors by

dividing the ripple current by the per−capacitor current

rating:

Number of capacitors + 13.347 A 2.397 A + 5.52

A total of at least 6 capacitors in parallel must be used to

meet the input capacitor ripple current requirements.

Output Switch FETs

Output switch FETs must be chosen carefully, since their

properties vary widely from manufacturer to manufacturer.

The CS5305 system is designed assuming that a FET driver

IC and n−channel FETs will be used. The FET

characteristics

most

concern

are

the

gate

charge/gate−source threshold voltage, gate capacitance,

on−resistance, current rating and the thermal capability of

the package.

FET driver ICs have a limited drive capability. If the

switch FET has a high gate charge, the amount of time the

FET stays in its ohmic region during the turn−on and

turn−off transitions is larger than that of a low gate charge

FET, with the result that the high gate charge FET will

consume more power. Similarly, a low on−resistance FET

will dissipate less power than will a higher on−resistance

FET at a given current. Thus, low gate charge and low

RDS(ON) will result in higher module efficiency and will

reduce heat being generated by the VRM module.

It can be advantageous to use multiple switch FETs to

reduce power consumption. By placing a number of FETs in

parallel, the effective RDS(ON) is reduced, thus reducing the

ohmic power loss. However, placing FETs in parallel

increases the gate capacitance so that switching losses

increase. As long as adding another parallel FET reduces the

ohmic power loss more than the switching losses increase,

there is some advantage to doing so. However, at some point

the law of diminishing returns will take hold, and a marginal

increase in efficiency may not be worth the board area

required to add the extra FET. Additionally, as more FETs

are used, the limited drive capability of the FET driver will

have to charge a larger gate capacitance, resulting in

increased gate voltage rise and fall times. This will affect the

amount of time the FET operates in its ohmic region and will

increase power dissipation.

The following equations can be used to calculate power

dissipation in the switch FETs.

For ohmic power losses due to RDS(ON):

PON(TOP) +

(RDS(ON)(TOP))(IRMS(TOP))2(n)

(number of topside FETs per phase)

PON(BOTTOM) +

RDS(ON)(BOTTOM) IRMS(BOTTOM) 2 n)

number of bottom−side FETs per phase

where:

n = number of phases.

Note that RDS(ON) increases with temperature. It is good

practice to use the value of RDS(ON) at the FET’s maximum

junction temperature in the calculations shown above.

IRMS(TOP) + I2PK * (IPK)(IRIPPLE) ) D3I

RIPPLE

IRMS(BOTTOM) + I2PK * (IPKIRIPPLE) )

(1 * D)

RIPPLE

IRIPPLE +

(VIN * VOUT)(VOUT)

(fOSC)(L)(VIN)

IPEAK + ILOAD )

IRIPPLE

IOUT

3 )

IRIPPLE

where:

D = Duty cycle.

For switching power losses:

PD + nCV2(fOSC)

where:

n = number of switch FETs (either top or bottom) per phase,

C = FET gate capacitance,

V = maximum gate drive voltage (usually VCC),

fOSC = switching frequency.

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