CS5305GDWR28 datasheet(20/33 Pages) ONSEMI

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CS5305

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PWRGD

0.975 × (VID − 125 mV)

1.975 V

VOUT

HIGH

LOW

PWRGD

−2.6% +2.6%

−5.0% +5.0%

Figure 33. PWRGD Assertion Window

low

PWRGD

low

PWRGD

high

In addition, certain fault modes must cause PWRGD to go

low to signal the system board that a VRM fault has

occurred. In that sense, the PWRGD signal operates as a

“VRM BAD” signal. These fault modes, as shown in Table 1

above, are ENABL low and CSx out of window.

When the ENABL pin is pulled low, PWRGD is pulled

low to indicate that the VRM is off. DRVON is pulled low

to turn both FETs off if the FET driver has an enable input.

The logic circuitry inside the chip sets PWRGD low only

after a delay period has been passed. A “power bad” event

does not cause PWRGD to go low unless it is sustained

through the delay time, typically 200 μs. If the anomaly

disappears before the end of the delay, the PWRGD output

will never be set low.

In order to use the PWRGD pin as specified, the user is

advised to connect external resistors as necessary to limit the

current into this pin to 4 mA or less.

Share Bus

VRM 9.x specifications require that a single−wire share

bus be provided from each module. This bus allows output

current information to be communicated between modules

such that the total load current is shared equally by each

module. The CS5305 employs a proprietary share algorithm

called direct duty cycle control. A block diagram is provided

in Figure 34.

PWM

LATCH

RESET

SET

GATEx

GATE

DRIVER

−

PWM

COMPARATOR

−

BUS AMP

− +

30 mV

−

ADJUST AMP

CURRENT

SENSE AMP

FROM

OSCILLATOR

COMP

SCOMP

IOUT

IFB

3.7× CURRENT

SENSE INPUT

3.3 V

VOUT + VOFFSET + 1× CURRENT SENSE INPUT

Figure 34.

Direct duty cycle control utilizes a master−slave approach

to current sharing. At any given current load, one module

will have a higher share bus voltage than the other modules.

This module acts as the master. It conveys output current

information to the other modules via the share bus. This

information is buffered and provided to the PWM

comparators, thus directly controlling duty cycle for the

slave modules.

The share current sense amplifier allows the user to

customize the share bus transconductance. Current sense

information is provided to the non−inverting input from the

3.7× current sense amplifier from each phase. This provides

a representation of the total module current. An external

resistor divider between IOUT and ground, center−tapped at

IFB programs the share bus voltage for a particular current

level.

The share bus amplifier serves as a buffer and places the

IOUT voltage on the SHARE pin. Note there is a diode in the

schematic between the share bus amplifier and the SHARE

pin. This is an “ideal” diode, and indicates that the share bus

amplifier does not have current sink capability. This allows

the share bus to be driven by the module with the highest

share bus voltage. A 30 mV offset voltage provides noise

immunity to ensure that any given module does not cycle

between master and slave in a random fashion. It also

guarantees that the master module is not driving duty cycle

from the share bus. For the master module, the IOUT and

SHARE voltages will be equal. In this case, the 30 mV offset

holds the share adjust amplifier inactive, and the PWM

channel is controlled in the normal manner. The offset

voltage results in a current error between the master and

slave modules, but this error is small compared to the current

share tolerance found in the VRM 9.x specifications.

The share adjust amplifier takes the share bus voltage and

directly drives the PWM comparators of all slave modules

as previously described. The SCOMP pin provides a

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