AD4080BBCZ datasheet(29/95 Pages) AD

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Data Sheet

AD4080

APPLICATIONS INFORMATION

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Rev. 0 | 29 of 95

REFERENCE CIRCUITRY DESIGN

The AD4080 requires a low noise, high precision and stability,

and low temperature drift external reference of 3 V. This reference

defines a differential input range for the ADC of ±VREFIN. The refer-

ence must be within ±5 mV of +3 V. Recommended references are

LTC6655, LT6657, or ADR4530. For best performance, however,

use the LTC6655 external reference. Table 13 details the typical

parameters of the previously mentioned references, comparing

absolute accuracy, noise, temperature drift, load regulation, and

power consumption. For more detailed specifications, refer to the

data sheet of the given product.

Table 13. Comparison of the Main Parameters of the LTC6655, LT6657, and

ADR4530 References

Parameter

LTC6655

LT6657

ADR4530B

Accuracy

0.025%

0.1%

0.02%

Temperature Coefficient

(ppm/ºC)

1.5

0.1 to 10 Hz Noise (ppm p-p)

0.25

0.5

0.53

Maximum Load (mA)

±5

±10

Load Regulation (ppm/mA)

0.7

Maximum Supply (V)

13.2

Shutdown

Yes

Supply Current, IS (mA)

1.2

0.7

There is no need for the external reference capacitor because

the AD4080 embeds one internally, 9.4 μF, (see Figure 45). The

REFIN reference input pin is internally buffered, which substantial-

ly reduces ADC conversion transients and isolates the external

reference from these transients. Therefore, no external amplifier is

required to buffer the external reference. For the reference input ca-

pacitance (C REF IN) and reference output capacitance (C REF OUT)

values, refer to the given external reference IC data sheet recom-

mendations. As a layout recommendation, the external reference

chip must be placed as close as possible to the AD4080 and its

REFIN pinto minimize the series impedance of the track connecting

the REFIN pin to the external reference output. It is recommended

to minimize the exposure of this track to noisy signals, especially

digital ones.

Figure 45. AD4080 General External Reference Design Functional Diagram

DATA INTERFACE CLOCKING SOLUTION

When designing the LVDS data interface (see the LVDS Data Inter-

face section), the user must ensure the clocking solution adheres

to the timing specifications of the AD4080 (see Table 2). When

configured for LVDS mode data interface, the user must ensure

that timing specifications stay within the maximum conversion to

clock alignment time of ±535 ps (tCCA). In addition, ensure that

a low jitter conversion (CNV) clock is provided such that there

is no unwanted impact to SNR performance. This jitter is signal

frequency dependent; therefore, the level of jitter tolerable in a

given system is dependent on the application use case. The Analog

Devices Technical Article Maximum SNR vs Clock Jitter provides

further guidance on this topic.

For example, a recommended clocking solution for where the

AD4080 is configured to use the LVDS data interface with a single

lane enabled and using echo clock mode. In this example, a 25

MHz oscillator is selected with low phase noise and jitter. The

following MT-008 tutorial serves as an aid to convert between

phase noise and RMS phase jitter, often quoted interchangeably

in crystal oscillator product data sheets. The ADF4350 wideband

synthesizer with an integrated voltage-controlled oscillator (VCO)

serves as versatile means of generating a 400 MHz clock system

clock, while maintaining low jitter and offering flexibility and control

to reconfigure this frequency depending on the application needs.

This clock then feeds the AD9508 clock fanout buffer with output

dividers that can be configured for the desired LVDS level signaling.

In the example shown in Figure 46, one output channel is set to

divide by 1 to output the LVDS clock, while another output channel

is configured to divide by 10 to output the AD4080 conversion

clock. This 1:10 ratio of CNV:CLK frequencies ensures 20 bits of

data can be read out in on the double data rate (DDR), single lane,

LVDS data interface. For a dual lane configuration, such as shown

in Figure 47, this ratio is adjust to 1:5.

The example shows that echo clock mode is used and aids data

alignment for the host controller (in the case a field-programmable

gate array (FPGA)). In self clock mode, where DCO+ and DCO−

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